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SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd v1.4 sn8p1900 series user?s manual SN8P1908 sn8p1909 s s o o n n i i x x 8 8 - - b b i i t t m m i i c c r r o o - - c c o o n n t t r r o o l l l l e e r r sonix reserves the right to make change without further notice to any products herein to improve reliability, function or desig n. sonix does not assume any liability arising out of the application or use of an y product or circuit described her ein; neither does it convey a ny license under its patent rights nor the rights of others. sonix products are not designed, intended, or authorized for us as components in systems inten ded, for surgical implant into the body, or other applications intended to suppor t or sustain life, or for any other application in which the fai lure of the sonix product could create a situation where personal injury or death may occu r. should buyer purchase or use sonix products for any such uni ntended or unauthorized application. buyer shall indemnify and hold sonix and its officers, employees, subs idiaries, affiliates and distri butors harmless against all claims, cost, damages, and expenses, and re asonable attorney fees arising out of, dire ctly or indirectly, any claim of pers onal injury or death associated with such unintended or unauthorized use even if such claim alleges that sonix was negligent regarding the design or manufacture of the part.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd v1.4 amendment history version date description pre v0.1 aug. 2003 preliminary v0.1 first issue pre v0.2 sep. 2003 1. rename avddr/avddcp/vcld1/avss 2 . modify application circuit. 3. change avddr to 3.8v 4 . port 2 is input only port 5. change SN8P1908 pin assignment pre v0.3 oct. 2003 1. modify register table 2. change SN8P1908 feature for 2-differential input 3. add x register 4. add adc note for stop mode or cpr off can?t input signal to analog channel. 5. add 80k adcks setting pre v0.4 oct. 2003 1. modify figure 13-1 ao+ to x+ 2. modify 2?s complement note2. 3. modify application circuit 4. modify application circuit (avddr) 5. change all gnd to vss pre v0.5 oct. 2003 1. change all gnd to vss 2. acm temp. coefficient = 50 ppm pre v0.6 oct. 2003 1. modify thermometer circuit 2. modify electrical characteristic 3. change cp/pgia/a dc clock calculate 4. fd[1:0] set as ?01? all the time 5. modify analog demo code pre v0.7 dec. 2003 1. change addr output as 3.8v and relative dc specification 2. modified dc spec. about current value. 3. pedge register ?01?, ?10? setting modified. pre v0.8 jan. 2004 1. bit drdy is r/w bit, remove note of dfm 2. add current note in cpm re gister for charge-pump enabled 3. connect vlcd1 to vlcd 4. change chopper frequency as 4k 5. add pgia output range in dc spec. 6. modified application circuit: vlcd and r+/r- 7. change charge pump frequency as 20k pre v0.9 jul. 2004 1. modified demo circui t for avddcp cap. ground to vss not avss. 2. add 100-ohm resistor in reset circuit. 3. modified demo circuit of avddcp to vss, voltage source r+/r- from e+
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 3 v1.4 4. add detail description of t0. v1.0 jan. 2005 1. modify sio descriptions and add sio timing chart. 2. modified cpcks clock table 3. change adenb to adcenb 4. correct fig-13-6 ai2-/ai3- 5. modified i/o diagram 6. add external low clock rc type oscillator circuit. 7. in electrical characteristic table: a. change ?vdd=3.8v? to ?avddr=3.8v? b. add r+/r- minimum differential voltage c. remove ?band gap reference? d. combine ?band gap reference? o perating current into ?charge pump regulator? quiescent current. change i qi from 300ua to 700ua e. modify some descriptions. v1.1 feb. 2005 1. b0mov m, i, m only supports 0x80~0x87 2. add note for push/pop only one level. 3. external reset circuit needs 100-ohm resistance. figure 6-4 v1.2 jun. 2005 1. change fds setting ?01? to ?01?. 2. update adc sample rate to 50 hz. 3. complete t0m description. 4. change demo code by xb0mov marco. 5. update fig-13-6/7/8 diagram. v1.3 sep. 2005 1. update fig-13-6/7/8 diagram. v1.4 sep. 2006 1. modified cpcks/ampcks/adcks as write mode register 2. limit the adc linear range as ? 28125 in adc chapter and elec. char. 3. add tc0 wake up from green mode
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 4 v1.4 table of contents amendment history .............................................................................................................. 2 1 1 1 product o verview ..................................................................................................... 8 general des cription ........................................................................................................... 8 features selecti on table ................................................................................................. 8 features....................................................................................................................... ............ 9 system block diagra m ...................................................................................................... 11 pin assign ment ................................................................................................................. .... 12 pin descri ptions ............................................................................................................... ... 14 pin circuit diagra ms .......................................................................................................... 1 5 2 2 2 code option table ................................................................................................... 16 3 3 3 address spa ces ........................................................................................................ 17 program memory (rom)..................................................................................................... 17 data memory (ram) .............................................................................................................. 25 working re gisters............................................................................................................. 2 7 program flag ................................................................................................................... .... 30 accumula tor .................................................................................................................... .... 31 stack oper ations............................................................................................................... .32 program co unter ............................................................................................................... 3 5 4 4 4 addressing mode...................................................................................................... 38 overview....................................................................................................................... .......... 38
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 5 v1.4 5 5 5 system regis ter ....................................................................................................... 40 overview....................................................................................................................... .......... 40 system register arrang ement (ban k 0) ..................................................................... 40 6 6 6 power on reset ........................................................................................................ 43 overview....................................................................................................................... .......... 43 external reset description........................................................................................... 44 low voltage detector (lvd) desc ription ................................................................. 45 7 7 7 oscillato rs................................................................................................................ 46 overview....................................................................................................................... .......... 46 system mode d escriptio n ................................................................................................ 52 system mode contro l ....................................................................................................... 53 wakeup time.................................................................................................................... ....... 55 8 8 8 timers co unters ....................................................................................................... 57 watchdog time r (wdt ) ....................................................................................................... 57 basic timer 0 (t0) ............................................................................................................. ..... 59 timer counter 0 (tc0 ) ......................................................................................................... 6 3 tc0out freque ncy tabl e.................................................................................................. 72 timer counter 1 (tc1 ) ......................................................................................................... 7 4 pwm function de scriptio n .............................................................................................. 83 9 9 9 interrup t..................................................................................................................... 8 7 overview....................................................................................................................... .......... 87
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 6 v1.4 inten interrupt en able regis ter ................................................................................. 88 intrq interrupt re quest regis ter.............................................................................. 88 interrupt operation descri ption ................................................................................ 89 1 1 1 0 0 0 serial input/output transceive r (sio).................................................. 98 overview....................................................................................................................... .......... 98 siom mode re gister.......................................................................................................... 100 siob data buff er ............................................................................................................... 101 sior register de scription ............................................................................................ 101 sio master operatin g descript ion ............................................................................ 102 sio slave operatin g descript ion................................................................................ 106 sio interrupt operation descript ion....................................................................... 111 1 1 1 1 1 1 i/o port ............................................................................................................. 112 overview....................................................................................................................... ........ 112 i/o port funct ion table .................................................................................................. 113 pull-up resistor (p n ur) registe r................................................................................ 113 i/o port mode .................................................................................................................. .... 114 the port2 dis cription ...................................................................................................... 115 i/o port data register .................................................................................................... 116 1 1 1 2 2 2 lcd drive r....................................................................................................... 117 lcdm1 re gister ................................................................................................................. .117 lcd ti ming ..................................................................................................................... ........ 119 lcd ram lo cation .............................................................................................................. 1 21 1 1 1 3 3 3 charge-pump, pgia and adc ..................................................................... 122 overview....................................................................................................................... ........ 122
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 7 v1.4 analog in put ................................................................................................................... .... 122 v oltage c harge p ump / r egulator (cpr) ............................................................................. 123 pgia -p rogrammable g ain i nstrumentation a mplifier .......................................................... 126 16-b it adc ............................................................................................................................ ... 131 1 1 1 4 4 4 application circuit ..................................................................................... 137 s cale (l oad c ell ) a pplication c ircuit ................................................................................... 137 t hermometer a pplication c ircuit .......................................................................................... 138 1 1 1 5 5 5 instruction set table ............................................................................... 139 1 1 1 6 6 6 electrical char acteristi c ..................................................................... 140 absolute maximu m rating .............................................................................................. 140 electrical chara cteristic ........................................................................................... 140 1 1 1 7 7 7 package info rmation ................................................................................ 142 lqfp64:........................................................................................................................ ............ 142 lqfp80......................................................................................................................... ............ 144
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 8 v1.4 1 1 1 product overview general description the sn8p1900 is a risc-like 8-bit mi cro-controller utilized cmos techno logy and featured with low power consumption and high performance by its unique electronic stru cture. the device is designed with the excellent ic structure including the program memory up to 8k-word ot p rom, data memory of 512-bytes ram, one 8-bit basic timer (t0) with rtc (real time clock) function, two 8-bi t timer counters (tc0, tc1), a watchdog timer, six interrupt sources (t0, tc0, tc1, sio, int0, int1), an 5-channel 16-bit adc converte r, programmable gain instrucmentation amplifier, charge pump, regulator, two channels pwm output (pwm0, pwm1), two channels buzzer output (bz0, bz1), 4-common by 32-segment lcd driver and 8-level stack buffe rs. there are four oscillator configurations to select for generating system clock, including high/low speed crystal, ceramic resonator or cost-saving rc. this device is a dual clock system using a hi-speed crystal for normal m ode operation and an external low speed 32.768khz crystal for slow mode, real time clock and lcd function features selection table timer chip rom ram stack lcd t0 tc0 tc1 i/o adc pwm buzzer sio wakeup pin no. package SN8P1908 8k*16 512*8 8 4*24 v v v 17 16-bit 2 - 7 lqfp64 sn8p1909 8k*16 512*8 8 4*32 v v v 20 16-bit 2 1 7 lqfp80 table 1-1 selection table of sn8p1900
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 9 v1.4 features SN8P1908 memory configuration otp rom size: 8k * 16 bits ram size: 512 * 8 bits (bank 0/1/2) 8-levels stack buffer lcd ram size: 4*24 bits i/o pin configuration input only: p0, p2 bi-directional: p1, p5 p2 shared with lcd segment wakeup: p0, p1 pull-up resisters: p0, p1, p2, p5 external interrupt: p0 powerful instructions four clocks per instruction cycle all instructions are one word length. most of instructions are 1 cycle only. maximum instructio n cycle is ?2?. jmp instruction jumps to all rom area. all rom area look-up table function (movc) support hardware multiplier (mul). programmable gain instrumentation amplifier gain option: 1/16/32/64/128 adc 16-bit delta-sigma adc with 14-bit noise free three adc channel configuration: 1. two fully differential input channels adc 2. one differential and two single channels adc 3. four single channels adc five interrupt sources three internal interru pts: t0, tc0, tc1 two external interrupts: int0, int1 1 real- time-clock timer with 0.5/1/2/4 second 1 eight-bit basic timer with green mode wakeup function 2 eight-bit timer counters with pwm or buzzer single power supply: 2.4v ~5.5v on-chip watchdog timer on-chip charge-pump regulator with 3.8v voltage output and 10ma driven current. on-chip 1.2v band gap reference for battery monitor. lcd driver: 1/3 or 1/2 bias voltage. 4 common * 24 segment dual clock system offers four operating modes external high clock: rc type up to 10 mhz external high clock: crystal type up to 16 mhz external low clock: crystal 32768hz normal mode: both high and low clock active. slow mode: low clock only. sleep mode: both high and low clock stop. green mode: periodical wakeup by timer. package lqfp64
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 10 v1.4 sn8p1909 memory configuration otp rom size: 8k * 16 bits ram size: 512 * 8 bits (bank 0/1/2) 8-levels stack buffer lcd ram size: 4*32 bits i/o pin configuration input only: p0, p2 bi-directional: p1, p5 p2 shared with lcd segment wakeup: p0, p1 pull-up resisters: p0, p1, p2, p5 external interrupt: p0 powerful instructions four clocks per instruction cycle all instructions are one word length. most of instructions are 1 cycle only. maximum instructio n cycle is ?2?. jmp instruction jumps to all rom area. all rom area look-up table function (movc) support hardware multiplier (mul). programmable gain instrumentation amplifier gain option: 1/16/32/64/128 adc 16-bit delta-sigma adc with 14-bit noise free three adc channel configuration: 1. three fully differential input channels adc 2. two differential and two single channels adc 3. one differential and four single channels adc six interrupt sources four internal interrupts: t0, tc0, tc1, sio two external interrupts: int0, int1 1 real- time-clock timer with 0.5/1/2/4 second 1 eight-bit basic timer with green mode wakeup function 2 eight-bit timer counters with pwm or buzzer single power supply: 2.4v ~5.5v on-chip watchdog timer on-chip charge-pump regulator with 3.8v voltage output and 10ma drive current. on-chip 1.2v band gap reference for battery monitor. sio function lcd driver: 1/3 or 1/2 bias voltage. 4 common * 32 segment dual clock system offers four operating modes external high clock: rc type up to 10 mhz external high clock: crystal type up to 16 mhz external low clock: crystal 32768hz normal mode: both high and low clock active. slow mode: low clock only. sleep mode: both high and low clock stop. green mode: periodical wakeup by timer. package lqfp80
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 11 v1.4 system block diagram figure 1-1 simplified system block diagram pc ir otp rom h-osc timing generator lcd driver ram system register alu acc interrupt control timer & counter port 0 port 1 port 2 port 5 seg. com . fla gs ? adc ai1~ai3 l-osc sio tx/rx pwm0 pwm1 pwm0/bu zzer0 pwm1/bu zzer1 charge pump avddcp pgia ao+, ao- pc ir otp rom h-osc timing generator lcd driver ram system register alu acc interrupt control interrupt control timer & counter port 0 port 1 port 2 port 5 seg. com . fla gs ? adc ai1~ai3 l-osc sio tx/rx sio tx/rx pwm0 pwm0 pwm1 pwm1 pwm0/bu zzer0 pwm1/bu zzer1 charge pump avddcp pgia ao+, ao-
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 12 v1.4 pin assignment SN8P1908 (lqfp64) com2 com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 com11 48seg14 com0 2 o 47seg15 vlcd 3 46vlcd1 r+4 45seg24/p2.0 r-5 44seg25/p2.1 x+6 43seg26/p2.2 x-7 42seg27/p2.3 ao+ 8 SN8P1908 41 seg28/p2.4 ao-9 40seg29/p2.5 ai2+ 10 39 seg30/p2.6 ai2- 11 38 seg31/p2.7 ai3+ 12 37 vss ai3-13 36p1.4 avss 14 35 p1.3 acm15 34p1.2 avddr16 33p1.1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 avddcp c+ vdd c- vss lxin lxout xin xout vdd p0.0/int0 p0.1/int1 p5.3/pwm1/bz1 p5.4/pwm0/bz0 vpp/rst p1.0
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 13 v1.4 sn8p1909 (lqfp80) com1 com2 com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 com0 1 o 60 seg17 vlcd 2 59 seg18 v3 3 58 seg19 v2 4 57 seg20 v1 5 56 seg21 r+ 6 55 seg22 r- 7 54 seg23 x+ 8 53 vlcd1 x- 9 52 seg24/p2.0 ao+ 10 51 seg25/p2.1 ao- 11 sn8p1909 50 seg26/p2.2 ai1+ 12 49 seg27/p2.3 ai1- 13 48 seg28/p2.4 ai2+ 14 47 seg29/p2.5 ai2- 15 46 seg30/p2.6 ai3+ 16 45 seg31/p2.7 ai3- 17 44 vss avss 18 43 p1.4 acm 19 42 p1.3 avddr 20 41 p1.2 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 avddcp c+ vdd c- vss lxin lxout xin xout vdd p0.0/int0 p0.1/int1 p5.0/sck p5.1/si p5.2/so p5.3/pwm1/bz1 p5.4/pwm0/bz0 vpp/rst p1.0 p1.1
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 14 v1.4 pin descriptions pin name type description vdd, vss, p power supply input pi ns for digital/analog circuit. vlcd1 p power supply of p2.0 ~ p2.7/ seg24~31. connect to vlcd vlcd p power supply of lcd v1~v3 p lcd bias voltage input avddr p regulator power output pin, vo ltage=3.8v maximum output current=10ma. avss p regulator analog ground. avddcp p charge pump voltage output. (connect a 2.2uf or higher capacitor to ground) acm p analog common voltage output, 1.2v r+ ai positive adc reference voltage input r- ai negative adc reference voltage input x+ ai positive adc differential input x- ai negative adc differential input ao+ ao positive amplifier output ao- ao negative amplifier output ai1+ ai positive analog input channel 1 ai1- ai negative analog input channel 1 ai2+ ai positive analog input channel 2 ai2- ai negative analog input channel 2 ai3+ ai positive analog input channel 3 ai3- ai negative analog input channel 3 c+ a positive capacitor terminal for charge pump regulator c- a negative capacitor terminal for charge pump regulator vpp/ rst p, i otp rom programming pin. system reset input pi n. schmitt trigger structure, active ?low?, normal stay to ?high?. xin, xout i, o external high clock oscillator pins. rc mode from xin. lxin, lxout i, o external low clock oscillator pins. rc mode from lxin. p0.0 / int0 i port 0.0 and shared with int0 trig ger pin (schmitt trigger) / built-in pull-up resisters. p0.1 / int1 i port 0.1 and shared with int1 trig ger pin (schmitt trigger) / built-in pull-up resisters. p1.0~p1.4 i/o port 1.0~port 1.4 bi-direction pi ns / wakeup pins/ built-in pull-up resisters. p2.0 ~ p2.7 i port 2.0~port 2.7 input port/ built-i n pull-up register and shared with lcd seg24~seg31. p5.0 / sck i/o port 5.0 bi-direction pin and sio? s clock input/output / built-in pull-up resisters. p5.1 / si i/o port 5.1 bi-direction pin and sio?s data input / built -in pull-up resisters. p5.2 / so i/o port 5.2 bi-direction pin and sio?s data output / built -in pull-up resisters. p5.3 / bz1 / pwm1 i/o port 5.3 bi-direction pin, tc1 signal out put pin for buzzer or pwm1 output pin. built-in pull-up resisters. p5.4 / bz0 / pwm0 i/o port 5.4 bi-direction pin, tc0 signal out put pin for buzzer or pwm0 output pin. built-in pull-up resisters. com [3:0] o lcd driver common port seg0 ~ seg31 o lcd driver segment pins. table 1-2 sn8p1900 pin description
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 15 v1.4 pin circuit diagrams port 1, port 5 structure figure 1-2. pin circuit diagram port0 structure pur p0ur pin int. bus pin int. bus pur port2 structure lcd waveform p2seg p2ur pin pin int. bus pur port2 structure pur port2 structure lcd waveform lcd waveform p2seg p2ur pull-up pin output latch pnm, pnur input bus pnm output bus
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 16 v1.4 2 2 2 code option table code option content function description rc low cost rc for external high clock oscillator 32k x?tal low frequency, power saving crystal (e.g. 32.768k) for external high clock oscillator 12m x?tal high speed crystal /resonator (e.g. 12m) for external high clock oscillator high_clk 4m x?tal standard crystal /resonator (e.g. 3.58m) for external high clock oscillator enable external high clock divided by two, f osc = high clock / 2 high_clk / 2 disable f osc = high clock enable enable oscillator safe guard function osg disable disable oscillator safe guard function enable enable watchdog function watch_dog disable disable watchdog function enable enable rom code security function security disable disable rom code security function 8-bit tc0 as 8-bit counter. 6-bit tc0 as 6-bit counter. 5-bit tc0 as 5-bit counter. tc0_count 4-bit tc0 as 4-bit counter. 8-bit tc1 as 8-bit counter. 6-bit tc1 as 6-bit counter. 5-bit tc1 as 5-bit counter. tc1_count 4-bit tc1 as 4-bit counter. enable enable noise filter function to enhance emi performance noise filter disable disable noise filter function always_on force watch dog timer clock source come from int 16k rc. a lso int 16k rc never stop both in power down and green mode that means watch dog timer will always enable both in power down and green mode. int_16k_rc by_cpum enable or disable internal 16k (@ 3v) rc clock by cpum register enable enable low power function to save operating current low power disable disable low power function table 2-1. code option table of sn8p1900 notice: in high noisy environment, enable ?noise filter?, ?osg? and disable ?low power? is strongly recommended. the side effect is to increase the lowest valid working voltage level if enable ?noise filter? or ?osg? or ?low power? code option. enable ?low power? option will reduce operating current except in 32k x?tal or slow mode. if users select ?32k x?tal? in ?high_clk? option, assembler will force ?osg? to be enabled. if users select ?rc? in ?high_clk? option, assembler will force ?high_clk / 2? to be enabled.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 17 v1.4 3 3 3 address spaces program memory (rom) overview rom maps for sn8p1900 devices provide 8k x 16 otp me mory that programmable by user. the sn8p1900 program memory is able to fetch instructions through 13-bit wide pc (program counter) and can look up rom data by using rom code registers (r, x, y, z). in st andard configuration, the devic e?s 8192 * 16-bit program memory has four areas: 1-word reset vector addresses 1-word interrupt vector addresses 5-words reserved area 8k words general purpose area all of the program memory is partitioned into two codi ng areas, located from 0000h to 0008h and from 0009h to 0ffeh. former area is assigned for executing reset ve ctor and interrupt vector. the later area is for storing instruction?s op-code and look-up t able?s data. user?s program is in the last area (0010h~1ffeh). rom 0000h reset vector user reset vector 0001h jump to user start address 0002h jump to user start address 0003h general purpose area jump to user start address 0004h 0005h 0006h 0007h reserved 0008h interrupt vector user interrupt vector 0009h user program . . 000fh 0010h 0011h . . 1ffeh general purpose area end of user program 1fffh reserved figure 3-1. rom address structure
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 18 v1.4 user reset vector address (0000h) a 1-word vector address area is used to execute system re set. after power-on reset or watchdog timer overflow reset, chip restarts the program from addre ss 0000h and all system registers will be set as default values. the following example shows the way to define the re set vector in the program memory. example: after power on reset, external reset active or reset by watchdog timer overflow. org 0 ; 0000h jmp start ; jump to user program address. . ; 0004h ~ 0007h are reserved org 10h start: ; 0010h, the head of user program. . ; user program . . . endp ; end of program interrupt vector address (0008h) a 1-word vector address area is used to execute interrupt re quest. if any interrupt servic e is executed, the program counter (pc) value is stored in stack buffer and points to 0008h of program memory to execute the vectored interrupt. users have to define the interr upt vector. the following example shows the wa y to define the interrupt vector in the program memory. example 1: this demo program includes interrupt service routine and the user program is behind the interrupt service routine. org 0 ; 0000h jmp start ; jump to user program address. . ; 0001h ~ 0007h are reserved org 8 ; interrupt service routine b0xch a, accbuf ; b0xch doesn?t change c, z flag push ; push 80h ~ 87h system registers . . . pop ; pop 80h ~ 87h system registers b0xch a, accbuf reti ; end of interrupt service routine start: ; the head of user program. . ; user program . . . jmp start ; end of user program endp ; end of program
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 19 v1.4 example 2: the demo program includes interrupt service routine and the address of interrupt service routine is in a special address of general-purpose area. org 0 ; 0000h jmp start ; jump to user program address. . ; 0001h ~ 0007h are reserved org 08 jmp my_irq ; 0008h, jump to interrupt service routine address org 10h start: ; 0010h, the head of user program. . ; user program . . . jmp start ; end of user program my_irq: ; label of interrupt service routine b0xch a, accbuf ; b0xch doesn?t change c, z flag push ; push 80h ~ 87h system registers . . . pop ; pop 80h ~ 87h system registers b0xch a, accbuf reti ; end of interrupt service routine endp ; end of program remark: it is easy to get the rules of sonix program from demo programs given above. these points are as following. 1. the address 0000h is a ?jmp? instruction to make the program go to general-purpose rom area. the 0004h~0007h are reserved. users have to skip 0004h~0007h addresses. it is very important and necessary. 2. the interrupt vector located at 0008h. users can put the whole interrupt service routine from 0008h (example1) or to put a ?jmp? instruction in 0008h then place the interrupt service routine in other general-purpose rom area (example2) to get modularized coding style.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 20 v1.4 checksum calculation the rom addresses 0004h~0007h and last address are reserved area. user shoul d avoid these addresses (0004h~0007h and last address) w hen calculate the checksum value. example: the demo program shows how to avoid 0004h~0007h when calculated checksum from 00h to the end of user?s code mov a, #end _user_code$l b0mov end_addr1,a ; save low end address to end_addr1 mov a,#end_user_code$m b0mov end_addr2,a ; save middle end address to end_addr2 clr y ; set y to 00h clr z ; set z to 00h @@: call yz_check ; call function of check yz value movc ; b0bset fc ;clear c flag add data1,a ;add a to data1 mov a,r adc data2,a ;add r to data2 jmp end_check ;check if the yz address = the end of code aaa: incms z ;z=z+1 jmp @b ;if z!= 00h calculate to next address jmp y_add_1 ;if z=00h increase y end_check: mov a,end_addr1 cmprs a,z ;check if z = low end address jmp aaa ;if not jump to checksum calculate mov a,end_addr2 cmprs a,y ;if yes, check if y = middle end address jmp aaa ;if not jump to checksum calculate jmp checksum_end ;if yes checksum calculated is done. yz_check: ;check if yz=0004h mov a,#04h cmprs a,z ;check if z=04h ret ;if not return to checksum calculate mov a,#00h cmprs a,y ;if yes, check if y=00h ret ;if not return to checksum calculate incms z ;if yes, increase 4 to z incms z incms z incms z ret ;set yz=0008h then return y_add_1: incms y ;increase y nop jmp @b ;jump to checksum calculate checksum_end: ???. ???. end_user_code: ; label of program end
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 21 v1.4 general purpose prog ram memory area the 8174-word at rom locations 0010h~1ffeh is used as general-purpose memory. the area stored instruction?s op-code and look-up table data. the sn8p1900 includes jump table function by using program counter (pc) and look-up table function by using rom code registers (r, x, y, z). the boundary of program memory is s eparated by the high-byte program counter (pch) every 100h. in jump table function and look-up table function, the program coun ter can?t leap over the boundary by program counter automatically. users need to modify the pch value to ?pch+1? as the pcl overflow (from 0ffh to 000h). look-up table description in the rom?s data look-up func tion, the x-register points to the highest 8-bit, y-register to the middle 8-bit and z-register to the lowest 8-bit data of rom address. after movc instruction exec uted, the low-byte data of rom stores in acc and high-byte data stores in r register. example: to look-up the rom data located ?table1?. b0mov y, #table1$m ; to set look-up table1?s middle address b0mov z, #table1$l ; to set look-up table1?s low address. movc ; to look-up data, r = 00h, acc = 35h ; ; increment the index address for next address incms z ; z+1 jmp @f ; not overflow incms y ; z overflow (ffh 00), y=y+1 nop ; not overflow ; @@: movc ; to look-up data, r = 51h, acc = 05h. . . ; table1: dw 0035h ; to define a word (16 bits) data. dw 5105h ; ? dw 2012h ; ? causion: the y-register can't increase automatical ly if z-register cross boundary from 0xff to 0x00. therefore, user must take care such situation to avoid loop-up table errors. if z-register overflows, y-register must be added by one. the following inc_yz macro shows a simple method to process y and z registers automatically. note: because the program counter (pc) is only 13-bit, the x register is useless in the application. users can omit ?b0mov x, #table1$h? . sonix ice support more larger program memory addressing capability. so make sure x register is ?0? to av oid unpredicted error in loop-up table operation. example: inc_yz macro inc_yz macro incms z ; z+1 jmp @f ; not overflow incms y ; y+1 nop ; not overflow @@: endm
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 22 v1.4 the other coding style of look-up table is to add y or z index register by accumulator. be careful if carry happens. refer the following example for detailed information: example: increase y and z register by b0add/add instruction b0mov y, #table1$m ; to set look-up table?s middle address. b0mov z, #table1$l ; to set look-up table?s low address. b0mov a, buf ; z = z + buf. b0add z, a b0bts1 fc ; check the carry flag. jmp getdata ; fc = 0 incms y ; fc = 1. y+1. nop getdata: ; movc ; to look-up data. if buf = 0, data is 0x0035 ; if buf = 1, data is 0x5105 ; if buf = 2, data is 0x2012 . . . . ; table1: dw 0035h ; to define a word (16 bits) data. dw 5105h ; ? dw 2012h ; ?
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 23 v1.4 jump table description the jump table operation is one of multi-address jumpin g function. add low-byte program counter (pcl) and acc value to get a new pcl. the new program counter (pc) points to a series jump in structions as a listing table. the way is easy to make a multi-branch program. when carry flag occurs after ex ecuting of ?add pcl, a?, it will not affect p ch register. users have to check if the jump table leaps over the rom page boundary or the listing file generated by sonix assembler. if the jump table leaps over the rom page boundary (e.g. from xxffh to xx00h), move t he jump table to the top of next program memory page (xx00h). here one page mean 256 words. example : if pc = 0323h (pch = 03h pcl = 23h) org 0x0100 ; the jump table is from the head of the rom boundary b0add pcl, a ; pcl = pcl + acc, the pch can?t be changed. jmp a0point ; acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point in following example, the jump table starts at 0x00fd. when executing ?b0add pcl, a?, acc = 0 or 1, the jump table points to the right address. if the acc is larger then 1 will cause error because pch doesn't increase one automatically. we can see the pcl = 0 when acc = 2 but the pch still keep in 0. the program counter (pc) will point to a wrong address 0x0000 and crash system operation. it is important to check whether the jump table crosses over the boundary (xxffh to xx00h). a good coding style is to put the jump table at the start of rom boundary (e.g. 0100h). example: errors occurs if jump table?s range over rom boundary. rom address . . . . . . 0x00fd b0add pcl, a ; pcl = pcl + ac c, the pch can?t be changed. 0x00fe jmp a0point ; acc = 0 0x00ff jmp a1point ; acc = 1 0x0100 jmp a2point ; acc = 2 jump table cross boundary here 0x0101 jmp a3point ; acc = 3 . . . . sonix provides a macro for safe jump table function. th is macro checks the rom boundary and move the jump table to the right position. the side effect of this macro is ma ybe wasting some rom size. notice the maximum jump table number for this macro is limited to 254. @jmp_a macro val if (($+1) !& 0xff00) !!= (($+(val)) !& 0xff00) jmp ($ | 0xff) org ($ | 0xff) endif add pcl, a endm note: ?val? is the number of the jump table listing number.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 24 v1.4 example: ?@jmp_a? application in sonix macro file called ?macro3.h?. b0mov a, buf0 ; ?buf0? is from 0 to 4. @jmp_a 5 ; the number of the jump table listing is five. jmp a0point ; if acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point jmp a4point ; acc = 4, jump to a4point if the jump table position is from 00fdh to 0101h, the ?@jmp_ a? macro will make the jump table to start from 0100h.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 25 v1.4 data memory (ram) overview the sn8p1900 has internally built-in data memory up to 512 bytes for storing general-purpose data and featured with lcd memory space up to 128 locations (4*32 bits) for displaying. 512 * 8-bit general purpose area 128 * 8-bit system register area 4*32* 8-bit lcd memory space these memories are separated into bank 0~3 and bank 15. the user can program rbank register of ram bank selection bit to access all data in any of the five ram banks. the bank 0~3 use the first 128-byte location assigned as general-purpose area, and the remaining 128-byte of bank 0 as system register. the bank 15 is lcd ram area designed for storing lcd display data. ram location 000h general purpose area ; 000h~07fh of bank 0 = to store general . ; purpose data (128 bytes). 07fh . 080h system register ; 080h~0ffh of bank 0 = to store system . ; registers (128 bytes). bank 0 0ffh end of bank 0 area 100h general purpose area ; bank 1 = to store general-purpose data. . bank 1 1ffh end of bank 1 area ; bank 1 had 256 bytes rams. bank 2 200h ? ; bank 2 = to store general-purpose data. ? 27fh ? ; bank 2 only had 128 bytes rams. ? ; 300h ? ; ? ? ; ? 380h ? ; ? ? ; ? f00h lcd ram area ; bank 15 = to store lcd display data . ; (32 bytes). bank 15 f1fh end of lcd ram ; figure 3-2 ram map of sn8p1900 note1: the undefined locations of system register ar ea are logic ?high? after executing read instruction ?mov a, m?. note2: the lower 32 locations of bank15 are used to store lcd display data and the other locations are reserved. the ram of lcd data area only use lowest 4-bit. the highest 4-bit are undefined.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 26 v1.4 ram bank selection the rbank is an 4-bit register located at 87h in ram bank 0. the user can access ram data by using this register pointing to working ram bank for acc to read/write ram data. rbank initial value = xxxx 0000 087h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rbank - - - - rbnks3 rbnks2 rbnks1 rbnks0 - - - - r/w r/w r/w r/w rbnk n : ram bank selecting control bit. 0 = bank 0, 1 = bank 1. example: ram bank selecting. ; bank 0 clr rbank . ; bank 1 mov a, #1 b0mov rbank, a . note: ?b0mov? instruction can access the ram of bank 0 in any rbank situation. example: access bank 0 data when rbank points to bank 1. ; bank 1 b0bset rbnks0 ; get into ram bank 1 b0mov a, buf0 ; read buf0 data. buf0 is in ram bank0. mov buf1, a ; write buf0 data to buf1. buf1 is in ram bank1. . . . mov a, buf1 ; read buf1 data and store in acc. b0mov buf0, a ; write acc data to buf0. when rbank points to bank 1, using ?b 0mov? instruction is an easy way to access ram bank 0 data. user can make a habit to read/write system register (0087h~00ffh). then user can access system registers without switching ram bank. example: to access the system registers when rbank points to bank 1. ; bank 1 b0bset rbnks0 ; get into ram bank 1 . . mov a, #0ffh ; set all pins of p1 to be logic high. b0mov p1, a . b0mov a, p0 ; read p0 data and store into buf1 of ram bank 1. mov buf1, a
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 27 v1.4 working registers the locations 80h to 86h of ram bank 0 stores the specially defined registers such as regist er h, l, r, x, y, z and pflag, respectively shown in the follo wing table. these registers can be t he general purpose of working buffer and also use to access rom?s and ram?s data. for instance, a ll of the rom?s table can be looked-up with r, x, y and z registers. the data of ram memory can be indire ctly accessed with h, l, y and z registers. 80h 81h 82h 83h 84h 85h 86h ram l h r z y x pflag r/w r/w r/w r/ w r/w r/w r/w h, l registers the h-register and l-register are 8-bit regi ster with two major functions. one is as working register and the other is to be data pointer to access ram?s data. the @hl located at address e6h in bank 0 is indirect data buffer. h and l register addresses ram location in order to read/write data through @hl. the lower 4-bit of h register is pointed to ram bank number and l register is pointed to ram address number, respectively. the higher 4-bit data of h register is truncated in ram indirectly access mode. h initial value = 0000 0000 081h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 h hbit7 hbit6 hbit5 hbit4 hbit3 hbit2 hbit1 hbit0 r/w r/w r/w r/w r/w r/w r/w r/w l initial value = 0000 0000 080h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 l lbit7 lbit6 lbit5 lbit4 lbit3 lbit2 lbit1 lbit0 r/w r/w r/w r/w r/w r/w r/w r/w example: reading a data from ram address 20h of ba nk 0, it can use indirectly addressing mode to access data as following. b0mov h, #00h ; to set ram bank 0 for h register b0mov l, #20h ; to set location 20h for l register b0mov a, @hl ; to read a data into acc example: clear general-purpose data memory area of bank 0 using @hl register. clr h ; h = 0, bank 0 mov a, #07fh b0mov l, a ; l = 7fh, the last address of the data memory area clr_hl_buf: clr @hl ; clear @hl to be zero decms l ; l ? 1, if l = 0, finish the routine jmp clr_hl_buf ; not zero clr @hl end_clr: ; end of clear general purpose data memory area of bank 0 . . . .
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 28 v1.4 y, z registers the y and z registers are 8-bit buffers. there are three majo r functions of these register s. first, y and z registers can be working registers. second, these two registers can be us ed as data pointers as @yz regi ster. third, the registers can be address rom location in order to look-up rom data. y initial value = 0000 0000 084h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 y ybit7 ybit6 ybit5 ybit4 ybit3 ybit2 ybit1 ybit0 r/w r/w r/w r/w r/w r/w r/w r/w z initial value = 0000 0000 083h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 z zbit7 zbit6 zbit5 zbit4 zbit3 zbit2 zbit1 zbit0 r/w r/w r/w r/w r/w r/w r/w r/w the @yz is data point_1 index buffer located at address e7h in ram bank 0. it employs y and z registers to addressing ram location in order to read/write data through @yz. the lower 4-bit of y register is pointed to ram bank number and z register is pointed to ram address number, respectively. the higher 4-bit data of y register is truncated in ram indirectly access mode. example: reading a data from ram address 25h of ba nk 1, it can use indirectly addressing mode to access data as following. b0mov y, #01h ; to set ram bank 1 for y register b0mov z, #25h ; to set location 25h for z register b0mov a, @yz ; to read a data into acc example: clear general-purpose data memory area of bank 1 using @yz register. mov a, #1 b0mov y, a ; y = 1, bank 1 mov a, #07fh b0mov z, a ; y = 7fh, the last address of the data memory area clr_yz_buf: clr @yz ; clear @yz to be zero decms z ; y ? 1, if y= 0, finish the routine jmp clr_yz_buf ; not zero clr @yz end_clr: ; end of clear general purpose data memory area of bank 0 .
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 29 v1.4 x registers there are two major functions of the x register. first, x r egister can be used as work ing registers. second, the x registers must be clear in order to look-up the rom data. the sn8p1700?s program counter only has 12-bit. in look-up table function, the users can omit x register. x initial value = 0000 0000 085h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x xbit7 xbit6 xbit5 xbit4 xbit3 xbit2 xbit1 xbit0 r/w r/w r/w r/w r/w r/w r/w r/w note: please consult the ?look-up table description? about x regist er look-up table application. r registers the r register is an 8-bit buffer. there are two major functions of the register. first, r register can be working registers. second, the r registers can be store high-byte data of look-up rom dat a. after movc instruction executed, the high-byte data of a rom address will stores in r register and the low-byte data in acc. r initial value = 0000 0000 082h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r rbit7 rbit6 rbit5 rbit4 rbit3 rbit2 rbit1 rbit0 r/w r/w r/w r/w r/w r/w r/w r/w
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 30 v1.4 program flag the pflag includes carry flag (c), decimal carry flag (dc) and zero flag (z). if the result of operating is zero or there is carry, borrow occurrence, then these flags will set to pflag register. pflag initial value = xxxx x000 086h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pflag nt0 npd - - - c dc z r/w r/w - - - r/w r/w r/w reset/wakeup flag nt0 npd description 0 0 watchdog timer overflow in sleep mode. in sleep mode must set ?int_16k_rc? code option as ?always_on? to enable watchdog timer. 0 1 watchdog timer overflow in normal/slow/green mode. 1 0 stop system clock (high or low clock) . there are two cases as following: 1. in normal mode: stop high clock or enter sleep mode (stphx=1 or cpum [1:0] = 01) 2. in slow mode: enter sleep mode (cpum [1:0] = 01) 1 1 external reset or lvd active note: watchdog timer is still running even ?watchdog? code option is disabled. user can disable watchdog code option then treat nt0/npd as another timer flag. carry flag c = 1: if executed arithmetic addition with occurring carry si gnal or executed arithmetic subtraction without borrowing signal or executed rotation instruction with shifting out logic ?1?. c = 0: if executed arithmetic addition wit hout occurring carry signal or executed arithmetic subtract ion with borrowing signal or executed rotation instruction with shifting out logic ?0?. decimal carry flag dc = 1: if executed arithmetic addition with occurring carry signal from low ni bble or executed arit hmetic subtraction without borrow signal from high nibble. dc = 0: if executed arithmetic addition wit hout occurring carry signal from low ni bble or executed arithmetic subtraction with borrow signal from high nibble. zero flag z = 1: after operation, the content of acc is zero. z = 0: after operation, the c ontent of acc is not zero.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 31 v1.4 accumulator the acc is an 8-bit data register responsible for trans ferring or manipulating data between alu and data memory. if the result of operation is zero (z) or carry (c or dc ) occurs, then these flags will set to pflag register. acc is not in data memory (ram), so acc can?t be acce ss by ?b0mov? instruction dur ing the instant addressing mode. example: read and write acc value. ; read acc data and store in buf data memory mov buf, a . . ; write a immediate data into acc mov a, #0fh . . ; write acc data from buf data memory mov a, buf . . push and pop instructions don?t store acc value as any in terrupt service executed. acc must be stored in another data memory defined by users. once interrupt occurs, t hese data must be stored in t he data memory based on the user?s program as follows. note: ?push?, ?pop? instructions only process 0x80~ 0x87 working registers a nd pflag register. users have to save and load acc by program as interrupt occurrence. example: protect acc and working registers. accbuf equ 00h ; accbuf is acc data buffer in bank 0. int_service: b0xch a, accbuf ; store acc value push. . ; push instruction . . . . pop ; pop instruction b0xch a, accbuf ; re-load acc reti ; exit interrupt service vector notice: to save and re-load acc data must be used ?b0xch? instruction, or the pflag value maybe modified by acc.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 32 v1.4 stack operations overview the stack buffer of sn8p1900 has 8-level high area and each level is 12-bit length. this buffer is designed to save and restore program counter (pc) data when in terrupt service executes. the stkp register is designed to point active level to save or restore data from stac k buffer for kernel circuit. the stk n h and stk n l are the 12-bit stack buffers to store program counter (pc) data. figure 3-3 stack-save and stack-restore operation stack buffer stk7h stk6h stk5h stk4h stk3h stk2h stk1h stk0h stk7l stk6l stk5l stk4l stk3l stk2l stk1l stk0l stkp = 0 stkp = 1 stkp = 2 stkp = 3 stkp = 4 stkp = 5 stkp = 6 stkp = 7 stkp - 1 stkp + 1 call / interrupt ret / reti stkp pch pcl stkp stack buffer stk7h stk6h stk5h stk4h stk3h stk2h stk1h stk0h stk7l stk6l stk5l stk4l stk3l stk2l stk1l stk0l stk7h stk6h stk5h stk4h stk3h stk2h stk1h stk0h stk7l stk6l stk5l stk4l stk3l stk2l stk1l stk0l stkp = 0 stkp = 1 stkp = 2 stkp = 3 stkp = 4 stkp = 5 stkp = 6 stkp = 7 stkp = 0 stkp = 1 stkp = 2 stkp = 3 stkp = 4 stkp = 5 stkp = 6 stkp = 7 stkp - 1 stkp + 1 stkp - 1 stkp - 1 stkp + 1 call / interrupt ret / reti stkp stkp pch pcl pch pch pcl pcl stkp stkp
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 33 v1.4 stack registers the stack pointer (stkp) is a 4-bit regi ster to store the address used to access the stack buffer, 12-bits data memory (stk n h and stk n l) set aside for temporary storage of stack addresses. the two stack operations write to the t op of the stack (stack-save) and read (sta ck-restore) from the top of stack. stack-save operation decreases the st kp and the stack-restore operation increas es one each time. that makes the stkp always points to the top address of stack buffer and writ es the last program counter value (pc) into the stack buffer. the program counter (pc) value is stored in the stack bu ffer before a call instruction ex ecuted or during interrupt service routine. stack operation is a lifo type (last in and first out). the stack pointer (stkp) and stack buffer (stk n h and stk n l) are located in the bank 0. stkp (stack pointer) initial value = 0xxx 1111 0dfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stkp gie - - - stkpb3 stkpb2 stkpb1 stkpb0 r/w - - - r/w r/w r/w r/w stkpb n : stack pointer. (n = 0 ~ 3) gie: global interrupt control bit. 0 = disable, 1 = enab le. more detail information is in interrupt chapter. example: stack pointer (stkp) reset routine. mov a, #00001111b b0mov stkp, a stk n (stack buffer) initial value = xxxx xxxx xxxx xxxx, stk n = stk n h + stk n l (n = 7 ~ 0) 0f0h~0ffh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stk n h - - - snpc12 snpc11 snpc10 snpc9 snpc8 - - r/w r/w r/ w r/w r/w r/w 0f0h~0ffh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stk n l snpc7 snpc6 snpc5 snpc4 snpc3 snpc2 snpc1 snpc0 r/w r/w r/w r/w r/w r/w r/w r/w stk n h: store pch data as interrupt or ca ll executing. the n expressed 0 ~7. stk n l: store pcl data as interrupt or ca ll executing. the n expressed 0 ~7.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 34 v1.4 stack operation example the two kinds of stack-save operations to reference the st ack pointer (stkp) and write the program counter contents (pc) into the stack buffer are call instru ction and interrupt service. under each condition, the stkp is decreased and points to the next available stack locati on. the stack buffer stores the program counter about the op- code address. the stack-save operation is as following table. stkp register stack buffer stack level stkpb3 stkpb2 stkpb1 stkpb0 high byte low byte description 0 1 1 1 1 stk0h stk0l - 1 1 1 1 0 stk1h stk1l - 2 1 1 0 1 stk2h stk2l - 3 1 1 0 0 stk3h stk3l - 4 1 0 1 1 stk4h stk4l - 5 1 0 1 0 stk5h stk5l - 6 1 0 0 1 stk6h stk6l - 7 1 0 0 0 stk7h stk7l - >8 - - - - - - stack overflow table 3-1. stkp, stk n h and stk n l relative of stack-save operation there is a stack-restore operation corres ponding each push operation to restore the program counter (pc). the reti instruction is for interrupt se rvice routine. the ret instruct ion is for call instruction. when a stack-restore operation executes the stkp increases and points to the next free st ack location. the stack buffer restores the last program counter (pc) to the program counter registers. the stack-restore operation is as following table. stkp register stack buffer stack level stkpb3 stkpb2 stkpb1 stkpb0 high byte low byte description 7 1 0 0 0 stk7h stk7l - 6 1 0 0 1 stk6h stk6l - 5 1 0 1 0 stk5h stk5l - 4 1 0 1 1 stk4h stk4l - 3 1 1 0 0 stk3h stk3l - 2 1 1 0 1 stk2h stk2l - 1 1 1 1 0 stk1h stk1l - 0 1 1 1 1 stk0h stk0l - table 3-2. stkp, stk n h and stk n l relative of stack-restore operation
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 35 v1.4 program counter the program counter (pc) is a 13-bit binary counter separat ed into the high-byte 5 bits and the low-byte 8 bits. this counter is responsible for pointing a location in order to fe tch an instruction for kernel circuit. normally, the program counter is automatically incremented with eac h instruction during program execution. besides, it can be replaced with specific address by execut ing call or jmp instruction. when jmp or call instruction is executed, the desti nation address will be inserted to bit 0 ~ bit 12. pc initial value = xxx0 0000 0000 0000 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pc - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 pch pcl pch initial value = xxxx 0000 0cfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pch - - - pc12 pc11 pc10 pc9 pc8 - - - r/w r/w r/w r/w r/w pcl initial value = 0000 0000 0ceh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pcl pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 r/w r/w r/w r/w r/w r/w r/w r/w
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 36 v1.4 one address skipping there are 9 instructions (cmprs, in cs, incms, decs, decms, bts0, bts1, b0bts0, b0bts1) with one address skipping function. if the result of these instructions is matched, the pc will add 2 steps to skip next instruction. if the condition of bit test instruction is matched, the pc will add 2 steps to skip next instruction. b0bts1 fc ; skip next instruction, if carry flag = 1 jmp c0step ; else jump to c0step. . c0step: nop b0mov a, buf0 ; move buf0 value to acc. b0bts0 fz ; skip next instruction, if zero flag = 0. jmp c1step ; else jump to c1step. . c1step: nop if the acc is equal to the immediat e data or memory, then pc will add 2 steps to skip next instruction. cmprs a, #12h ; skip next instruction, if acc = 12h. jmp c0step ; else jump to c0step. . c0step: nop if the result after increasing 1 or decreasing 1 is 0xffh (for decs and decms) or 0x00h (for incs and incms) , the pc will add 2 steps to skip next instruction. incs instruction: incs buf0 ; skip next instruction, if buf0 = 0x00h. jmp c0step ; else jump to c0step. . c0step: nop incms instruction: incms buf0 ; skip next instruction, if buf0 = 0x00h. jmp c0step ; else jump to c0step. . c0step: nop decs instruction: decs buf0 ; skip next instruction, if buf0 = 0xffh. jmp c0step ; else jump to c0step. . c0step: nop decms instruction: decms buf0 ; skip next instruction, if buf0 = 0xffh. jmp c0step ; else jump to c0step. . c0step: nop
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 37 v1.4 multi-address jumping user can jump round multi-address by ei ther jmp instruction or ?add pcl, a? instruction to activate multi-address jumping function. if carry signal occurs after execution of ?add pcl, a?, the carry signal will not affect pch register. example: if pc = 0323h (pch = 03h pcl = 23h) ; pc = 0323h mov a, #28h b0mov pcl, a ; jump to address 0328h . . . . ; pc = 0328h . . mov a, #00h b0mov pcl, a ; jump to address 0300h example: if pc = 0323h (pch = 03h pcl = 23h) ; pc = 0323h b0add pcl, a ; pcl = pcl + acc, the pch cannot be changed. jmp a0point ; if acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 38 v1.4 4 4 4 addressing mode overview the sn8p1900 provides three addressing modes to access ram data, including immediate addressing mode, directly addressing mode and indirectly address mode. the main pur pose of the three different modes is described in the following: immediate addressing mode the immediate addressing mode uses an immediate data to set up the location (mov a, #i, b0mov m, #i) in acc or specific ram. immediate addressing mode mov a, #12h ; to set an immediate data 12h into acc directly addressing mode the directly addressing mode uses address number to access memory location (mov a, 12h, mov 12h,a). directly addressing mode b0mov a, 12h ; to get a content of location 12h of bank 0 and save in acc indirectly addressing mode the indirectly addressing mode is to set up an address in dat a pointer registers (y/z) and uses mov instruction to read/write data between acc and @yz r egister (mov a, @yz, mov @yz, a). example: indirectly addressing mode with @yz register clr y ; to clear y register to access ram bank 0. b0mov z, #12h ; to set an immediate data 12h into z register. b0mov a, @yz ; use data pointer @yz reads a data from ram location ; 012h into acc. mov a, #01h b0mov y, a ; to set y = 1 for accessing ram bank 1. b0mov z, #12h ; to set an immediate data 12h into z register. b0mov a, @yz ; use data pointer @yz reads a data from ram location ; 012h into acc. mov a, #0fh b0mov y, a ; to set y = 15 for accessing ram bank 15. b0mov z, #12h ; to set an immediate data 12h into z register. b0mov a, @yz ; use data pointer @yz reads a data from ram location 012h ; into acc.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 39 v1.4 to access data in ram bank 0 in the ram bank 0, this area memory can be read/written by these three access methods. example 1: to use ram bank0 dedicate instruction (such as b0xxx instruction). b0mov a, 12h ; to move content from location 12h of ram bank 0 to acc example 2: to use direct addressing mode (through rbank register). b0mov rbank, #00h ; to set ram bank = 0 mov a, 12h ; to move content from location 12h of ram bank 0 to acc example 3: to use indirectly a ddressing mode with @yz register. clr y ; to clear y register for accessing ram bank 0. b0mov z, #12h ; to set an immediate data 12h into z register. b0mov a, @yz ; use data pointer @yz reads a data from ram location ; 012h into acc. to access data in ram bank 1 in the ram bank 1, this area memory can be read/written by these two access methods. example 1: to use directly addressing mode (through rbank register). b0mov rbank, #01h ; to set ram bank = 1 mov a, 12h ; to move content from location 12h of ram bank 1 to acc example 2: to use indirectly a ddressing mode with @yz register. mov a, #01h b0mov y, a ; to set y = 1 for accessing ram bank 1. b0mov z, #12h ; to set an immediate data 12h into z register. b0mov a, @yz ; use data pointer @yz reads a data from ram location ; 012h into acc. to access data in ram bank 15 (lcd ram) in the ram bank 15, this area memory can be read/written by these two access methods. example 1: to use directly addressing mode (through rbank register). b0mov rbank,#0fh ; to set ram bank = 15 mov a,12h ; to move content from location 12h of ram bank 15 to acc example 2: to use indirectly a ddressing mode with @yz register. mov a,#0fh b0mov y,a ; to set y = 15 for accessing ram bank 15. b0mov z,#12h ; to set an immediate data 12h into z register. b0mov a,@yz ; use data pointer @yz reads a data from ram location 012h into acc.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 40 v1.4 5 5 5 system register overview the ram area located in 80h~ffh bank 0 is system register area. the main purpose of system regist ers is to control peripheral hardware of the chip. using system registers can control i/o ports, sio, adc, pwm, lcd, timers and counters by programming. the memory map provides an easy and quick reference source for writing application program. to access these system regi sters is controlled by the select me mory bank (rbank = 0) or the bank 0 read/write instruction (b 0mov, b0bset, b0bclr?). system register arrangement (bank 0) bytes of system register sn8p1900 0 1 2 3 4 5 6 7 8 9 a b c d e f 8 l h r z y x pflag rbank option lcdm1 - - - - - - 9 ampm ampchs ampcks adcm adcks cpm cpcks dfm adcdl adcdh - - - - - - a - - - - - - - - - - - - - - - - b - - - - siom sior siob - - - - - - - - pedge c p1w p1m - - p5m - - intrq inten oscm - - tc0r pcl pch d p0 p1 p2 - - p5 - - t0m t0c tc0m tc0c tc1m tc1c tc1r stkp e p0ur p1ur p2ur - - p5ur @hl @yz - - - - - - - - f stk7 stk7 stk6 stk6 stk5 stk5 stk4 st k4 stk3 stk3 stk2 stk2 stk1 stk1 stk0 stk0 table 5-1. ram register arrangement of sn8p1900 description l, h = working & @hl addressing register r = working register and rom look-up data buffer y, z = working, @yz and rom addressing register option= rtc and rclk options. pflag = rom page and special flag regi ster rbank= ram bank select register ampm = pgia mode register ampchs = pgia channel selection ampcks = pgia clock selection adcm = adc?s mode register adcks = adc clock selection cpm = charge pump mode cpcks = charge pump clock selection dfm = decimation filter mode adcdl = adc low-byte data buffer adcdh = adc high-byte data buffer siom = sio mode control register sior = sio clock reload buffer siob = sio data buffer p1w = port 1 wakeup register p n m = port n input/output mode register p n ur = port n pull-up register p n = port n data buffer intrq = interrupt request register inten = interrupt enable register oscm = oscillator mode register lcdm1= lcd mode register pch, pcl = program counter t0m = timer 0 mode register tc0m = timer/counter 0 mode register t0c = timer 0 counting register tc0c = timer/counter 0 counting register tc1m = timer/counter 1 mode register tc0r = timer/counter 0 auto-reload data buffer tc1c = timer/counter 1 counting register stkp = stack pointer buffer stk0~stk7 = stack 0 ~ stack 7 buffer @hl = ram hl indirect addressing index pointer @yz = ram yz indirect addressing index pointer
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 41 v1.4 bits of system register address bit7 bit6 bit5 bit4 bi t3 bit2 bit1 bit0 r/w name 080h lbit7 lbit6 lbit5 lbit4 lbit3 lbit2 lbit1 lbit0 r/w l 081h hbit7 hbit6 hbit5 hbit4 hbit3 hbit2 hbit1 hbit0 r/w h 082h rbit7 rbit6 rbit5 rbit4 rbit3 rbit2 rbit1 rbit0 r/w r 083h zbit7 zbit6 zbit5 zbit4 zbit3 zbit2 zbit1 zbit0 r/w z 084h ybit7 ybit6 ybit5 ybit4 ybit3 ybit2 ybit1 ybit0 r/w y 085h xbit7 xbit6 xbit5 xbit4 xbit3 xbit2 xbit1 xbit0 r/w x 086h nt0 npd - - - c dc z r/w pflag 087h - - - - rbnks3 rbnks2 rbnks1 rbnks0 r/w rbank 088h - - - - rtcm1 rtcm0 - rclk r/w option 089h - - lcdbnk - lcdenb bias p2seg r/w lcdm1 090h - - fd1 fd0 gs2 gs1 gs0 ampenb r/w ampm 091h - - - - - chs2 chs1 chs0 r/w ampchs 092h ampcks7 ampcks6 ampcks5 ampcks4 ampcks3 ampcks2 ampcks1 ampcks0 w ampcks 093h - - - - - rvs1 rvs0 adcenb r/w adcm 094h adcks7 adcks6 adcks5 adcks4 adcks3 adcks2 adcks1 adcks0 w adcks 095h - - - - cpsts cpauto cpon cprenb r/w cpm 096h cpcks7 cpcks6 cpcks5 cpcks4 cpcks3 cpcks2 cpcks1 cpcks0 w cpcks 097h - - wrs1 wrs0 stod drdy r/w dfm 098h adcb7 adcb6 a dcb5 adcb4 adcb3 adcb2 a dcb1 adcb0 r adcdl 099h adcb15 adcb14 a dcb13 adcb12 adcb11 adcb 10 adcb9 adcb8 r adcdh 0b4h senb start srate1 srate0 sig sckmd sedge txrx r/w siom 0b5h sior7 sior6 sior5 sior4 sior3 sior2 sior1 sior0 w sior 0b6h siob7 siob6 siob5 siob4 siob3 siob2 siob1 siob0 r/w siob 0bfh pedgen - - p00g1 p00g0 - - - r/w pedge 0c0h - - - p14w p13w p12w p11w p10w w p1w 0c1h - - - p14m p13m p12m p11m p10m r/w p1m 0c5h - - - p54m p53m p52m p51m p50m r/w p5m 0c8h - tc1irq tc0irq t0irq sioirq - p01irq p00irq r/w intrq 0c9h - tc1ien tc0ien t0ien sioen - p01ien p00ien r/w inten 0cah wtcks wdrst wdarte cpum1 cpum0 clkmd stphx - r/w oscm 0cdh tc0r7 tc0r6 tc0r5 tc0r4 tc0r3 tc0r2 tc0r1 tc0r0 w tc0r 0ceh pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 r/w pcl 0cfh - - - pc12 pc11 pc10 pc9 pc8 r/w pch 0d0h - - - - - - p01 p00 r p0 0d1h - - - p14 p13 p12 p11 p10 r/w p1 0d2h p27 p26 p25 p24 p23 p22 p21 p20 r p2 0d5h - - - p54 p53 p52 p51 p50 r/w p5 0d8h t0enb t0rate2 t0rate1 t0rate0 tc1x8 tc0x8 tc0gn t0tb r/w t0m 0d9h t0c7 t0c6 t0c5 t0c4 t0c3 t0c2 t0c1 t0c0 r/w t0c 0dah tc0enb tc0rate2 tc0rate1 tc0rate0 tc0cks aload0 tc0out pwm0out r/w tc0m 0dbh tc0c7 tc0c6 tc0c5 tc0c4 tc0c3 tc0c2 tc0c1 tc0c0 r/w tc0c 0dch tc1enb tc1rate2 tc1rate1 tc1rate0 tc1cks aload1 tc1ou t pwm1out r/w tc1m 0ddh tc1c7 tc1c6 tc1c5 tc1c4 tc1c3 tc1c2 tc1c1 tc1c0 r/w tc1c 0deh tc1r7 tc1r6 tc1r5 tc1r4 tc1r3 tc1r2 tc1r1 tc1r0 w tc1r 0dfh gie - - - stkpb3 stkpb2 stkpb1 stkpb0 r/w stkp 0e0h - - - - - - p01r p00r w p0ur 0e1h - - - p14r p13r p12r p11r p10r w p1ur 0e2h p27r p26r p25r p24r p23r p22r p21r p20r w p2ur 0e5h - - - p54r p53r p52r p51r p50r w p5ur 0e6h @hl7 @hl6 @hl5 @hl4 @h l3 @hl2 @hl1 @hl0 r/w @hl 0e7h @yz7 @yz6 @yz5 @yz4 @yz3 @yz2 @yz1 @yz0 r/w @yz (to be continued)
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 42 v1.4 address bit7 bit6 bit5 bit4 bi t3 bit2 bit1 bit0 r/w remarks 0f0h s7pc7 s7pc6 s7pc5 s7pc4 s7pc3 s7pc2 s7pc1 s7pc0 r/w stk7l 0f1h - - - s7pc12 s7pc11 s7pc10 s7pc9 s7pc8 r/w stk7h 0f2h s6pc7 s6pc6 s6pc5 s6pc4 s6pc3 s6pc2 s6pc1 s6pc0 r/w stk6l 0f3h - - - s6pc12 s6pc11 s6pc10 s6pc9 s6pc8 r/w stk6h 0f4h s5pc7 s5pc6 s5pc5 s5pc4 s5pc3 s5pc2 s5pc1 s5pc0 r/w stk5l 0f5h - - - s5pc12 s5pc11 s5pc10 s5pc9 s5pc8 r/w stk5h 0f6h s4pc7 s4pc6 s4pc5 s4pc4 s4pc3 s4pc2 s4pc1 s4pc0 r/w stk4l 0f7h - - - s4pc12 s4pc11 s4pc10 s4pc9 s4pc8 r/w stk4h 0f8h s3pc7 s3pc6 s3pc5 s3pc4 s3pc3 s3pc2 s3pc1 s3pc0 r/w stk3l 0f9h - - - s3pc12 s3pc11 s3pc10 s3pc9 s3pc8 r/w stk3h 0fah s2pc7 s2pc6 s2pc5 s2pc4 s2pc3 s2pc2 s2pc1 s2pc0 r/w stk2l 0fbh - - - s2pc12 s2pc11 s2pc10 s2pc9 s2pc8 r/w stk2h 0fch s1pc7 s1pc6 s1pc5 s1pc4 s1pc3 s1pc2 s1pc1 s1pc0 r/w stk1l 0fdh - - - s1pc12 s1pc11 s1pc10 s1pc9 s1pc8 r/w stk1h 0feh s0pc7 s0pc6 s0pc5 s0pc4 s0pc3 s0pc2 s0pc1 s0pc0 r/w stk0l 0ffh - - - s0pc12 s0pc11 s0pc10 s0pc9 s0pc8 r/w stk0h table 5-2. bit system register table note: a). all of register names had been declared in sn8asm assembler. b). one-bit name had been declared in sn8asm assembler with ?f? prefix code. c). it will get logic ?h? data, when u se instruction to check empty location. d). the low nibble of adr register is read only. e). ?b0bset?, ?b0bclr?, ?bset?, ?bclr? of in structions just only support ?r/w? registers. f). for detail description please refer file of ?system register quick reference table?
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 43 v1.4 6 6 6 power on reset overview sn8p1900 provides two system resets. o ne is external reset and the other is low voltage detector (lvd). the external reset is a simple rc circuit connecting to the reset pin. t he low voltage detector (lvd) is built in internal circuit. when one of the reset devices occurs, the system will reset and the system registers become initial value. the timing diagram is as following. vdd external reset internal reset signal end of lvd reset lvd end of external reset lvd detect level external reset detect level figure 6-1 power on reset timing diagram
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 44 v1.4 external reset description the external reset is a low level active device. the rese t pin receives the low voltage and resets the system. when the voltage detects high level, it stops rese tting the system. users can use an exter nal reset circuit to control system operation. it is necessary that the vdd must be stable. external reset vdd internal reset signal external reset detect level end of external reset system reset figure 6-2 external reset timing diagram users must to be sure the vdd stable earlier than external rese t (figure 6-2) or the external reset will fail. the external reset circuit is a simple rc circuit as following. figure 6-3. external reset circuit gnd vcc rst vdd mcu vss r 20k ohm c 0.1uf 100 ohm r
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 45 v1.4 in worse power condition as brown out reset. the reset pin may keep high level but the vdd is low voltage. that makes the system reset fail and chip error. to connect a diode from reset pin to vdd is a good solution. the circuit can force the capacitor to release electric charge and drop the voltage, and solve the error. figure 6-4. external reset circuit with diode low voltage detector (lvd) description the lvd is a low voltage detector. it detects vdd level an d reset the system as the vdd lower than the desired voltage. the detect level is 1.8v. if the vdd lower than 1.8v , the system resets. the lvd function is controlled by code option. users can turn on it for specia l application like worse power condition. lv d work with external reset function. they are or active. system reset lvd detect level end of lvd reset vdd lvd figure 6-5. lvd timing diagram note: lvd is always enable in sn8p1900 series mcu vdd vss vcc gnd rst r 20k ohm c 0.1uf diode 100-ohm
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 46 v1.4 7 7 7 oscillators overview the sn8p1900 highly performs the dual clock micro-controller system. t he dual clocks are high-speed clock and low-speed clock. the high-speed clock frequency is suppli ed through the external oscillator circuit. the low-speed clock frequency is supplied through external low clock oscillator (32.768k) by crystal or rc mode. because real-time-clock (rtc) used low-spee d clock for timer, 32768hz x?tal usually used for low-speed clock to an exact real-time-clock . the external high-speed clock and the extern al low-speed clock can be system clock (f osc ). the system clock is divided by 4 to be the instruction cycle (f cpu ). f cpu = f osc / 4 the system clock is required by the following peripheral modules: basic timer (t0) timer counter 0 (tc0) timer counter 1 (tc1) watchdog timer serial i/o interface (sio) ad converter pwm output (pwm0out, pwm1out) buzzer output (tc0out, tc1out) clock block diagram fl cpum0 lxosc. fcpu fosc/4 cpum0 fh hxosc. xin xout stphx hxrc cpum0 divided by 4 clkmd divided by 2 osg divided by 2 1 : disable 0 : enable osg : oscillator safe guard 1 : disable -- system default 0 : enable hxrc(1:0) is code option ?00= rc ?01 =32 khz oscillator ?10 = high speed oscillator (>10mhz) ?11 = standard oscillator (4mhz) fl cpum0 lxosc. fl cpum0 lxosc. fcpu fosc/4 cpum0 fcpu fosc/4 cpum0 fh hxosc. xin xout stphx hxrc cpum0 fh hxosc. xin xout stphx hxrc cpum0 divided by 4 clkmd divided by 4 divided by 4 clkmd divided by 2 divided by 2 osg osg divided by 2 1 : disable 0 : enable osg : oscillator safe guard 1 : disable -- system default 0 : enable hxrc(1:0) is code option ?00= rc ?01 =32 khz oscillator ?10 = high speed oscillator (>10mhz) ?11 = standard oscillator (4mhz) figure 7-1. clock block diagram hxosc: external high-speed clock. lxosc: external low-speed clock. osg: oscillator safe guard.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 47 v1.4 oscm register description the oscm register is an oscillator control register. it can co ntrol oscillator select, system mode, watchdog timer clock source and rate. oscm initial value = 0000 0000 0cah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 oscm wtcks wdrst wdrate cpum1 cpum0 clkmd stphx - r/w r/w r/w r/ w r/w r/w r/w - stphx: eternal high-speed oscillator cont rol bit. 0 = free run, 1 = stop. this bit just only controls external high-speed oscillator. if stphx=1, the external lo w-speed rc oscillator is still running. clkmd: system high/low speed mode select bi t. 0 = normal (dual) mode, 1 = slow mode. cpum1,cpum0: cpu operating mode control bit. 00=normal, 01 = sleep (power down) mode to turn off both high/low clock, 10=green mode, 11=reserved wtcks: watchdog clock source select bit. 0 = f cpu , 1 = internal rc low clock. option register description option initial value = xxxx 00x0 088h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 option - - - - rtcm1 rtcm0 - rclk - - - - r/w r/w - r/w rclk: external low oscillator type control bit. 0 = crystal mode 1 = rc mode. note1: circuit diagram when rclk=0 ?external low clock sets as crystal mode.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 48 v1.4 note2: circuit diagram when ?rclk=1? will enable external low clock sets as rc mode. connect the c as near as possible to the vss pin of micro-controller. the freque ncy of external low rc is decided by the capacitor value. adjust capacitor value to about 32khz frequency. rtcm [1:0] : real time clock mode setting bits. there are 4 types rtc timing, 0.5/1/2/4 second. rtcm1 rtcm0 rtc time (second) 0 0 0.5 0 1 1 1 0 2 1 1 4 note1: bit t0tb control t0 as normal timer or real time clock. note2: s8kd-2 ice can simulate 0.5 second rtc only. the others timers are valid by real chip.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 49 v1.4 external high-speed oscillator sn8p1900 can be operated in four diffe rent oscillator modes. there are external rc os cillator modes, high crystal/resonator mode (12m code option), standard crys tal/resonator mode (4m code option) and low crystal mode (32k code option). for different applicat ion, the users can select one of sati able oscillator mode by programming code option to generate system high-s peed clock source after reset. example: stop external high-speed oscillator. b0bset fstphx ; to stop exter nal high-speed oscillator only. b0bset fcpum0 ; to stop external high- speed oscillator and ex ternal low-speed ; oscillator called powe r down mode (sleep mode). oscillator mode code option sn8p1900 has four oscillator modes for different app lications. these modes are 4m, 12m, 32k and rc. the main purpose is to support different oscillator types and frequen cies. high-speed crystal needs more current but the low one doesn?t. for crystals, there are three steps to select. if the o scillator is rc type, to select ?rc? and the system will divide the frequency by 2 automatically. user can select oscillator mode from code option table before compiling. the table is as follow. code option oscillator mode remark 00 rc mode output the f cpu square wave from x out pin. 01 32k 32768hz 10 12m 12mhz ~ 16mhz 11 4m 3.58mhz oscillator devide by 2 code option sn8p1900 has an external clock divide by 2 function. it is a code option called ?high_clk / 2?. if ?high_clk / 2? is enabled, the external clock frequency is divided by 8 for the f cpu . f cpu is equal to fosc/8. if ?high_clk / 2? is disabled, the external clock frequency is divided by 4 for the f cpu . the f cpu is equal to fosc/4. note: in rc mode, ?high_clk / 2? is always enabled. oscillator safe guard code option sn8p1900 builds in an oscillator safe guard (osg) to make os cillator more stable. it is a low-pass filter circuit and stops high frequency noise into system fr om external oscillator circuit. this func tion makes system to work better under ac noisy conditions.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 50 v1.4 system oscillator circuits mcu xin vdd xout vss crystal 20pf 20pf figure 7-2. crystal/ceramic oscillator mcu xin vdd vss xout c r figure 7-3. rc oscillator xin vdd mcu vss xout external clock input figure 7-4. external clock input note1: the vdd and vss of external oscillator circuit mu st be from micro-contro ller. don?t connect them from power terminal. note2: the external clock input mode can select rc type oscillator or cr ystal type oscillator of the code option and input the external clock into xin pin. note3: in rc type oscillator code option situation, the external clock?s freq uency is divided by 2. note4: the power and ground of external oscillator circ uit must be connected fr om the micro-controller?s vdd and vss. it is necessary to step up the performance of the whole system.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 51 v1.4 external rc oscillator frequency measurement there are two ways to get the f osc frequency of external rc oscillator. one measures the xout output waveform. under external rc oscillator mode, the xout out puts the square waveform whose frequency is f cpu . the other measures the external rc frequ ency by instruction cycle (f cpu ). the external rc frequency is the f cpu multiplied by 4. we can get the f osc frequency of external rc from the f cpu frequency. the sub-routine to get f cpu frequency of external oscillator is as the following. example: f cpu instruction cycle of external oscillator b0bset p1m.0 ; set p1.0 to be output mode for outputting f cpu toggle signal. @@: b0bset p1.0 ; output f cpu toggle signal in low-speed clock mode. b0bclr p1.0 ; measure the f cpu frequency by oscilloscope. jmp @b
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 52 v1.4 system mode description overview the chip is featured with low power consumption by switching around three different modes as following. high-speed mode low-speed mode power-down mode (sleep mode) green mode in actual application, the user can adjust the chip?s controller to work in these four modes by using oscm register. at the high-speed mode, the instruction cycle (f cpu ) is fosc/4. at the low-speed mode and 3v, the f cpu is 16khz/4. normal mode in normal mode, the system clock source is external hi gh-speed clock. after power on, the system works under normal mode. the instruction cycle is fosc/4. when the external hi gh-speed oscillator is 3.58mhz, the instruction cycle is 3.58mhz/4 = 895khz. all software and hardware are executed and working. in normal mode, system can get into power down mode, slow mode and green mode. slow mode in slow mode, the system clock source is external low-speed rc clock. to set clkmd = 1, the system switches into slow mode. in slow mode, the system works as normal mo de but the clock slower. the system in slow mode can get into normal mode, power down mode and green mode. to set stphx = 1 to stop the external high-speed oscillator, and then the system consumes less power. green mode the green mode is a less power consumption mode. under green mode, there are only t0/tc0 still counting and the other hardware stop ping. the external high-sp eed oscillator or exter nal low-speed oscillator is operating. to set cpum1 = 1 and cpum0 = 0, the system get s into green mode. the system can be waked up to last system mode by t0 timer timeout and p0, p1 trigger signal. the green mode provides a time-variable wakeup function. users can decide wakeup time by setting t0/tc0 timer. there are two channels into green mode. one is normal mo de and the other is slow mode. in normal mode, the t0/tc0 timers overflow time is very short. in slow mode, the overflow time is longer. users can select appropriate situation for their applications. under green mode, the power consumpt ion is 5u amp in 3v condition. sleep (power down) mode the power down mode is also called sleep mode. the chip stops working as sleeping status. the power consumption is very less almost to zero. the power down mode is usua lly applied to low power consum ing system as battery power productions. to set cupm0 = 1, the system gets into power down mode. the external high-speed and low-speed oscillators are turned off. the system c an be waked up by p0, p1 trigger signal.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 53 v1.4 system mode control sn8p1900 system mode block diagram figure 7-5. sn8p1900 system mode block diagram mode normal slow green sleep remark hx osc. running by stphx by stphx stop lx osc. running running running stop cpu instruction executi ng executing stop stop t0 timer *active *act ive *active inactive tc0 timer *active *act ive *active inactive tc1 timer *active *active inactive inactive * active by program watchdog timer active active inactive inactive internal interrupt all active all active t0/tc0 all inactive external interrupt all active all active all active all inactive wakeup source - - port0, port1, t0/tc0, reset p0, p1, reset table 7-1. oscillator oper ating mode description note: in the green mode, t0 trigger signals can switch cpu return to the last mode. if the system was into green mode from normal mode, the system returns to normal mode. if the system was into green mode from slow mode, the system returns to slow mode. normal mode green mode slow mode power down mode (sleep mode) p0, p1 wake-up function active. external reset circuit active. cpum1, cpum0 = 01 clkmd = 0 clkmd = 1 cpum1, cpum0 = 10 p0, p1 wake-up function active. t0, tc0 time out. p0, p1 wake-up function active. t0, tc0 time out. external reset circuit active. external reset circuit active. normal mode green mode slow mode power down mode (sleep mode) p0, p1 wake-up function active. external reset circuit active. cpum1, cpum0 = 01 clkmd = 0 clkmd = 1 cpum1, cpum0 = 10 p0, p1 wake-up function active. t0, tc0 time out. p0, p1 wake-up function active. t0, tc0 time out. external reset circuit active. external reset circuit active.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 54 v1.4 system mode switching normal/slow mode to power down (sleep) mode. cpum0 = 1 ) b0bset fcpum0 ; set cpum0 = 1. note: in normal mode and slow mode, the cpum1 = 0 and can omit to set cpum1 = 0 routine. normal mode to slow mode. b0bset fclkmd ;to set clkmd = 1 b0bset fstphx ;to stop exter nal high-speed oscillator. note: to stop high-speed oscillator is not necessary and us er can omit it. switch slow mode to normal mode (the ext ernal high-speed oscillator is still running) b0bclr fclkmd ;to set clkmd = 0 switch slow mode to normal mode ( the external high-speed oscillator stops) if external high clock stop and program want to switch back normal mode. it is necessary to delay at least 10ms for external clock stable. b0bclr fstphx ; turn on the external high-speed oscillator. b0mov z, #27 ; if vdd = 5v, internal rc=32khz (typical) will delay @@: decms z ; 0.125ms x 81 = 10.125ms for external clock stable jmp @b ; b0bclr fclkmd ; change the system back to the normal mode normal/slow mode to green mode. cpum1, cpum0 = 10 system can return to the last mode by p0, p1 and t0 wakeup function. example: go into green mode. b0bset fcpum1 ; to set cpum1, cpum0 = 10 note: in normal mode or slow mode, the cpum0 = 0 and can omit to set cpum0 = 0 routine. example: go into green mode and enable t0 wakeup function. ; set t0 timer wakeup function. b0bclr ft0ien ; to disable t0 interrupt service b0bclr ft0enb ; to disable t0 timer mov a,#20h ; b0mov t0m,a ; to set t0 clock = f cpu / 64 mov a,#74h b0mov t0c,a ; to set t0c initial val ue = 74h (to set t0 interval = 10 ms) b0bclr ft0ien ; to disable t0 interrupt service b0bclr ft0irq ; to clear t0 interrupt request b0bset ft0enb ; to enable t0 timer ; go into green mode b0bclr fcpum0 ;to set cpum x = 10 b0bset fcpum1 note: if t0enb = 0, t0 is without wakeup from green mode to normal/slow mode function.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 55 v1.4 wakeup time overview the external high-speed oscillator needs a delay time fr om stopping to operating. the del ay is very necessary and makes the oscillator to work stably. so me conditions during system operating, the external hi gh-speed oscillator often runs and stops. under these conditions, the delay time for ex ternal high-speed oscillator restart is called wakeup time. there are two conditions need wakeup time. one is power down mode to normal mode. the other one is slow mode to normal mode. for the first case, sn8p1900 provides 2048 oscillat or clocks to be the wakeup time. however, in the last case, users need to make the wakeup time by themselves. hardware wakeup when the system is in power down mode (sleep mode), the external high-speed oscillator stops. when waked up from power down mode, mcu waits for 2048 exter nal high-speed oscillator clocks as the wakeup time to stable the oscillator circuit. after the wakeup time, the system goes into the normal mode. the value of the wakeup time is as the following. the wakeup time = 1/fosc * 2048 (sec) + x?tal settling time the x?tal settling time is depended on the x?tal type. typically, it is about 2~4ms. example: in power down mode (sleep mode), the syst em is waked up by p0 or p1 trigger signal. after the wakeup time, the system goes into normal mode. the wakeup time of p0, p1 wakeup function is as the following. the wakeup time = 1/fosc * 2048 = 0.57 ms (fosc = 3.58mhz) the total wakeup time = 0.57ms + x?tal settling time under power down mode (sleep mode), there are only i/o ports with wakeup function wake the system up to normal mode. the port 0 and port 1 have wakeup function. port 0 wa keup function always enables, but the port 1 is controlled by the p1w register. p1w initial value = xx00 0000 0c0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1w - - - p14w p13w p12w p11w p10w - - - w w w w w p10w~p14w: port 1 wakeup function control bits. 0 = none wakeup function 1 = enable each pin of port 1 wakeup function.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 56 v1.4 external wakeup trigger control in the sn8p1909/SN8P1908, the wakeup trigger direction is control by pedge register. pedge initial value = 0xx0 0xxx 0bfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pedge pedgen - - p00g1 p00g0 - - - r/w - - r/w r/w - - - bit7 pedgen: interrupt and wakeup trigger edge control bit. 0 = disable edge trigger function. port 0: low-level wakeup trigger and falling edge interrupt trigger. port 1: low-level wakeup trigger. 1 = enable edge trigger function. p0.0: both wakeup and interrupt trigger are controlled by p00g1 and p00g0 bits. p0.1: both wakeup and interrupt trigger are level change (falling or rising edge). port 1: wakeup trigger is level change (falling or rising edge). bit[4:3] p00g[1:0]: port 0.0 edge select bits. 00 = reserved, 01 = falling edge, 10 = rising edge, 11 = rising/falling bi-direction.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 57 v1.4 8 8 8 timers counters watchdog timer (wdt) the watchdog timer (wdt) is a binary up counter designed fo r monitoring program execution. if the program runs into the unknown status by noise in terference, wdt overflow signal will reset th is chip and restart operation. the instruction that clears the watchdog timer (b0bset fwdrst) should be ex ecuted at proper points in a program within a given period. if an instruction that clears the watchdog timer is not executed within the period and the watchdog timer overflows, reset signal is generated and system is restart ed with reset status. in order to generate different output timings, the user can control watchdog timer by modifying wdrate control bit of oscm register. the watchdog timer will be disabled at green and power do wn modes. oscm initial value = 0000 000x 0cah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 oscm wtcks wdrst wdrate cpum1 cpum0 clkmd stphx - r/w r/w r/w r/ w r/w r/w r/w - bit1 stphx: external high-speed os cillator control bit. 0 = free run, 1 = stop. note: this bit only controls extern al high-speed oscillator. if stph x=1, the internal low-speed rc oscillator is still running. bit2 clkmd: system high/low speed mode select bit. 0 = normal (dual) mode, 1 = slow mode. bit [4:3] cpum [1:0] : cpu operating mode control bit. 00 = normal, 01 = sleep (power down) mode, 10 = green mode, 11 = reserved. bit5 wdrate: watchdog timer rate select bit. 0 = f cpu 2 14 1 = f cpu 2 8 bit6 wdrst: watchdog timer reset bit. 0 = no reset 1 = clear the watchdog timer?s counter. (the detail information is in watchdog timer chapter.) bit7 wtcks: watchdog clock source select bit. 0 = f cpu 1 = internal rc low clock. wtcks wtrate clkmd watchdog timer overflow time 0 0 0 1 / (f cpu 2 14 16) = 293 ms, f osc =3.58mhz 0 1 0 1 / (f cpu 2 8 16) = 500 ms, f osc =32768hz 0 0 1 1 / (f cpu 2 14 16) = 32s, f osc =32768hz 0 1 1 1 / (f cpu 2 8 16) = 500 ms, f osc =32768hz 1 - - 1 / (32768 512 16) ~ 0.25s table 8-1. watchdog timer overflow time table
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 58 v1.4 note: the watchdog timer can be enabled or disabled by the code option. example: an operation of watchdog timer is as following. to clear the watchdog timer?s counter in the top of the main routine of the program. main: b0bset fwdrst ; clear the watchdog timer?s counter. . . call sub1 call sub2 . . . . . . jmp main
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 59 v1.4 basic timer 0 (t0) overview the basic timer (t0) is an 8-bit binary up counter. it uses t0m register to select t0c?s input clock for counting a precision time. if the t0 timer has occur an overflow (from ffh to 00h), it will continue counting and issue a time-out signal to trigger t0 interrupt to request interrupt service. the main purposes of the t0 basic timer is as following. 8-bit programmable timer: generates interrupts at specific time inte rvals based on the selected clock frequency. figure 8-2. basic timer t0 block diagram t0m register description the t0m is the basic timer mode register which is a 8-bit read/write register and only used the high nibble. by loading different value into the t0m register, users can modify t he basic timer clock dynamically as program executing. eight rates for t0 timer can be selected by t0rate0 ~ t0ra te2 bits. the range is from fcpu/2 to fcpu/256. the t0m initial value is zero and the rate is fcpu/256. the bit7 of t0m called t0enb is the control bit to start t0 timer. the combination of these bits is to determine t he t0 timer clock frequency and the intervals. t0m initial value = 0000 xxxx 0d8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t0m t0enb t0rate2 t0rate1 t0rate0 tc1x8 tc0x8 tc0gn t0tb r/w r/w r/w r/w r/w r/w r/w r/w bit7 t0enb: t0 timer control bit. 0 = disable 1 = enable. bit[6:4] t0rate2~t0rate0: the t0 timer?s clock source selects bits. t0rate [2:0] tc0 clock source 000 f cpu /256 001 f cpu /128 ? ? 110 f cpu /4 111 f cpu /2 bit3 tc1x8 : multiple tc1 timer speed eight times. refe r tc1m register for detailed information. 0 = tc1 clock came from fcpu 1 = tc1 clock came from fosc bit2 tc0x8 : multiple tc0 timer speed eight times. refe r tc0m register for detailed information. 0 = tc0 clock came from fcpu 1 = tc0 clock came from fosc t0enb t0c 8-bit binary counter t0 time out pre_load internal data bus 2 (8-t0rate) f cpu t0enb t0c 8-bit binary counter t0 time out pre_load internal data bus 2 (8-t0rate) f cpu
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 60 v1.4 bit1 tc0gn: enable tc0 green mode wakeup function 0 = disable 1 = enable bit0 t0tb: timer 0 as the real-time clock time base. 0 = timer 0 function as a normal timer system. 1 = timer 0 function as a real-time clock. the clock so urce of timer 0 will be switched to external low clock (32.768k crystal oscillator).
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 61 v1.4 t0c counting register t0c is an 8-bit counter register for the basic timer (t0). t0 c must be reset whenever the t0enb is set ?1? to start the basic timer. t0c is incremented by on e with every clock pulse which frequency is determined by t0rate0 ~ t0rate2. when t0c has incremented to ?0ffh?, it will be cleared to ?00h? in next clock and an overflow generated. under t0 interrupt service request (t0ien) enable condition, the t0 interrupt request flag will be set ?1? and the system executes the interrupt service routine. the t0c has no auto reload fu nction. after t0c overflow, the t0c is continuing counting. users need to reset t0c value to get a accurate time. t0c initial value = xxxx xxxx 0d9h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t0c t0c7 t0c6 t0c5 t0c4 t0c3 t0c2 t0c1 t0c0 r/w r/w r/w r/w r/w r/w r/w r/w high speed mode (fcpu = 3.58mhz / 4) low speed mode (fcpu = 32768hz / 4) t0rate t0clock max overflow interval one step = max/256 max overflow interval one step = max/256 000 fcpu/256 73.2 ms 286us 8000 ms 31.25 ms 001 fcpu/128 36.6 ms 143us 4000 ms 15.63 ms 010 fcpu/64 18.3 ms 71.5us 2000 ms 7.8 ms 011 fcpu/32 9.15 ms 35.8us 1000 ms 3.9 ms 100 fcpu/16 4.57 ms 17.9us 500 ms 1.95 ms 101 fcpu/8 2.28 ms 8.94us 250 ms 0.98 ms 110 fcpu/4 1.14 ms 4.47us 125 ms 0.49 ms 111 fcpu/2 0.57 ms 2.23us 62.5 ms 0.24 ms figure 8-3. the timing table of basic timer t0. the equation of t0c initial value is as following. t0c initial value = 256 - (t0 interrupt interval time * input clock) example : to set 10ms interval time for t0 interrupt at 3.58mhz high-speed mode. t0c value (74h) = 256 - (10ms * fcpu/64) t0c initial value = 256 - (t0 interrupt interval time * input clock) = 256 - (10ms * 3.58 * 10 6 / 4 / 64) = 256 - (10 -2 * 3.58 * 10 6 / 4 / 64) = 116 = 74h
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 62 v1.4 t0 basic timer operation sequence the t0 basic timer?s sequence of operation can be following. set the t0c initial value to setup the interval time. set the t0enb to be ?1? to enable t0 basic timer. t0c is incremented by one with each clock pulse wh ich frequency is corresponding to t0m selection. t0c overflow when t0c from ffh to 00h. when t0c overflow occur, the t0irq flag is set to be ?1? by hardware. execute the interrupt service routine. users reset the t0c value and resu me the t0 timer operation. example: setup the t0m and t0c. b0bclr ft0ien ; to disable t0 interrupt service b0bclr ft0enb ; to disable t0 timer mov a,#20h ; b0mov t0m,a ; to set t0 clock = fcpu / 64 mov a,#74h b0mov t0c,a ; to set t0c initial val ue = 74h (to set t0 interval = 10 ms) b0bset ft0ien ; to enable t0 interrupt service b0bclr ft0irq ; to clear t0 interrupt request b0bset ft0enb ; to enable t0 timer example: t0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; store acc value. b0mov a, pflag b0mov pflagbuf, a ; save pflag register in a buffer b0bts1 ft0irq ; check t0irq jmp exit_int ; t0irq = 0, exit interrupt vector b0bclr ft0irq ; reset t0irq mov a,#74h ; reload t0c b0mov t0c,a . . ; t0 interrupt service routine . . jmp exit_int ; end of t0 interrupt se rvice routine and exit interrupt vector . . . . exit_int: b0mov a, pflagbuf b0mov pflag, a ; restore pflag register from buffer b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 63 v1.4 timer counter 0 (tc0) overview the timer counter 0 (tc0) is used to generate an interrupt r equest when a specified time interval has elapsed. tc0 has an auto re-loadable counter that consists of two parts: an 8-bi t reload register (tc0r) into which you write the counter reference value, and an 8-bit counter register (tc0c) whos e value is automatically incremented by counter logic. figure 8-1. timer count tc0 block diagram the main purposes of the tc0 timer counter is as following. 8-bit programmable timer: generates interrupts at specific time inte rvals based on the selected clock frequency. arbitrary frequency output (buzzer output): outputs selectable clock frequencies to the bz0 pin (p5.4). pwm function: pwm output can be generated by the pwm1out bit and output to pwm0out pin (p5.4). tc0r reload data buffer fcpu tc0enb tc0c 8-bit binary counter tc0 time out load aload0 auto. reload p5.4 ? 2 tc0out internal p5.4 i/o circuit cpum 0 s r compar e pw m0 o ut pw m buzzer 2 ( 8- tc0rate) int0 (schmitter trigger) tc0cks tc0r reload data buffer fcpu tc0enb tc0c 8-bit binary counter tc0 time out load aload0 auto. reload p5.4 ? 2 tc0out internal p5.4 i/o circuit cpum 0 s r compar e pw m0 o ut pw m buzzer 2 ( 8- tc0rate) int0 (schmitter trigger) tc0cks
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 64 v1.4 tc0m mode register the tc0m is the timer counter mode regi ster, which is an 8-bit read/write register. by loading different value into the tc0m register, users can modify the timer counter clock frequency dynamically when program executing. eight rates for tc0 timer can be selected by tc0rate0 ~ tc0rate2 and tc0x8 bit of t0m register. if tc0x8=1 the tc0 will faster 8 times than tc0x8 = 0(initial value). the 7 th bit of tc0m named tc0enb is the control bit to start tc0 timer. tc0m initial value = 0000 0000 0dah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0m tc0enb tc0rate2 tc0r ate1 tc0rate0 tc0cks aloa d0 tc0out pwm0out r/w r/w r/w r/w r/w r/w r/w r/w bit7 tc0enb: tc0 counter/bz0/pwm0out enable bit. 0 = disable, 1 = enable. bit[6:4] tc0rate[2:0]: tc0 clock source selection bits. tc0x8 is 2 nd bit of t0m register tc0 clock source tc0rate [2:0] tc0x8 = 0 tc0x8 = 1 000 f cpu /256 = f osc /1024 f osc /128 001 f cpu /128 = f osc /512 f osc /64 ? ? ? 110 f cpu /4 = f osc /16 f osc /2 111 f cpu /2 = f osc /8 f osc note: f cpu = f osc / 4 bit3 tc0cks: tc0 clock source select bit. 0 = f cpu , 1 = external clock comes from int0/p0.0 pin. bit2 aload0: tc0 auto-reload function control bit. 0 = none auto-reload, 1 = auto-reload. bit1 tc0out: tc0 time-out toggle signal output control bit. 0 = to disable tc0 signal output and to enable p5.4?s i/o function, 1 = to enable tc0?s signal output and to disable p5.4?s i/o function. (auto-disable the pwm0out function.) bit0 pwm0out: tc0?s pwm output control bit. 0 = to disable the pwm output, 1 = to enable the pwm output (the tc0out control bit must = 0 ) note: when tc0cks=1, tc0 became an external event c ounter. no more p0.0 interrupt request will be raised. (p00irq will be always 0)
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 65 v1.4 tc0c counting register tc0c is an 8-bit counter register for the timer counter (tc0 ). tc0c must be reset whenever the tc0enb is set ?1? to start the timer counter. tc0c is incremented by one wi th a clock pulse which the frequency is determined by tc0rate0 ~ tc0rate2. wh en tc0c has incremented to ?0ffh?, it is will be cleared to ?00h? in next clock and an overflow is generated. under tc0 interrupt service request (tc0ien) enable condition, the tc0 interrupt request flag will be set ?1? and the system executes the interrupt service routine. tc0c initial value = xxxx xxxx 0dbh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0c tc0c7 tc0c6 tc0c5 tc0c4 tc0c3 tc0c2 tc0c1 tc0c0 r/w r/w r/w r/w r/w r/w r/w r/w tc0 overflow time tc0 rate is determinate by tc0rate and code option tc 0_counter, tc0rate can set tc0 clock frequency and tc0_counter set tc0 became 8-bi t, 6-bit, 5-bit or 4-bit counter. the equation of tc0c initial value is as following. tc0c initial value = n - (tc0 interrupt interval time * input clock) which n is determinate by code option: tc0_counter tc0_counter n max. tc0c value 8-bit 256 255 6-bit 64 63 5-bit 32 31 4-bit 16 15 note: thetc0c must small or equal than max. tc0 value. example: to set 10ms interval time for tc0 interrupt at f osc = 3.58mhz. tc0c value (74h) = 256 - (10ms * f cpu /64) (tc0rate=010, tc0_counter=8-bit, tc0x8=0) tc0c initial value = 256 - (tc0 inte rrupt interval time * input clock) = 256 - (10ms * 3.58 * 10 6 / 4 / 64) = 256 - (10 -2 * 3.58 * 10 6 / 4 / 64) = 116 = 74h example: to set 1.25ms interval time for tc0 interrupt at f osc = 3.58mhz. tc0c value (74h) = 256 - (10ms * f cpu /64) (tc0rate=010, tc0_counter=8-bit, tc0x8=1) tc0c initial value = 256 - (tc0 inte rrupt interval time * input clock) = 256 - (1.25ms * 3.58 * 10 6 / 32) = 256 - (0.00125 * 3.58 * 10 6 / 32) = 116 = 74h example: to set 1ms interval time for tc0 interrupt at f osc = 3.58mhz. tc0c value (32h) = 64 - (1ms * f cpu /64) (tc0rate=010, tc0_counter=6-bit, tc0x8=0) tc0c initial value = 64 - (tc0 interrupt interval time * input clock) = 64 - (1ms * 3.58 * 10 6 / 4 / 64) = 64 - (1 -2 * 3.58 * 10 6 / 4 / 64) = 64-14 = 32h
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 66 v1.4 tc0_counter=8-bit, tc0x8=0 high speed mode (f cpu = 3.58mhz / 4) low speed mode (f cpu = 32768hz / 4) tc0rate tc0clock max overflow interval one step = max/256 ma x overflow interval one step = max/256 000 f cpu /256 73.2 ms 286us 8000 ms 31.25 ms 001 f cpu /128 36.6 ms 143us 4000 ms 15.63 ms 010 f cpu /64 18.3 ms 71.5us 2000 ms 7.8 ms 011 f cpu /32 9.15 ms 35.8us 1000 ms 3.9 ms 100 f cpu /16 4.57 ms 17.9us 500 ms 1.95 ms 101 f cpu /8 2.28 ms 8.94us 250 ms 0.98 ms 110 f cpu /4 1.14 ms 4.47us 125 ms 0.49 ms 111 f cpu /2 0.57 ms 2.23us 62.5 ms 0.24 ms tc0_counter=6-bit , tc0x8=0 high speed mode (f cpu = 3.58mhz / 4) low speed mode (f cpu = 32768hz / 4) tc0rate tc0clock max overflow interval one step = max/64 ma x overflow interval one step = max/64 000 f cpu /256 18.3 ms 286us 2000 ms 31.25 ms 001 f cpu /128 9.15 ms 143us 1000 ms 15.63 ms 010 f cpu /64 4.57 ms 71.5us 500 ms 7.8 ms 011 f cpu /32 2.28 ms 35.8us 250 ms 3.9 ms 100 f cpu /16 1.14 ms 17.9us 125 ms 1.95 ms 101 f cpu /8 0.57 ms 8.94us 62.5 ms 0.98 ms 110 f cpu /4 0.285 ms 4.47us 31.25 ms 0.49 ms 111 f cpu /2 0.143 ms 2.23us 15.63 ms 0.24 ms tc0_counter=5-bit, tc0x8=0 high speed mode (f cpu = 3.58mhz / 4) low speed mode (f cpu = 32768hz / 4) tc0rate tc0clock max overflow interval one step = max/32 ma x overflow interval one step = max/32 000 f cpu /256 9.15 ms 286us 1000 ms 31.25 ms 001 f cpu /128 4.57 ms 143us 500 ms 15.63 ms 010 f cpu /64 2.28 ms 71.5us 250 ms 7.8 ms 011 f cpu /32 1.14 ms 35.8us 125 ms 3.9 ms 100 f cpu /16 0.57 ms 17.9us 62.5 ms 1.95 ms 101 f cpu /8 0.285 ms 8.94us 31.25 ms 0.98 ms 110 f cpu /4 0.143 ms 4.47us 15.63 ms 0.49 ms 111 f cpu /2 71.25 us 2.23us 7.81 ms 0.24 ms tc0_counter=4-bit, tc0x8=0 high speed mode (f cpu = 3.58mhz / 4) low speed mode (f cpu = 32768hz / 4) tc0rate tc0clock max overflow interval one step = max/16 ma x overflow interval one step = max/16 000 f cpu /256 4.57 ms 286us 500 ms 31.25 ms 001 f cpu /128 2.28 ms 143us 250 ms 15.63 ms 010 f cpu /64 1.14 ms 71.5us 125 ms 7.8 ms 011 f cpu /32 0.57 ms 35.8us 62.5 ms 3.9 ms 100 f cpu /16 0.285 ms 17.9us 31.25 ms 1.95 ms 101 f cpu /8 0.143 ms 8.94us 15.63 ms 0.98 ms 110 f cpu /4 71.25 us 4.47us 7.81 ms 0.49 ms 111 f cpu /2 35.63 us 2.23us 3.91 ms 0.24 ms
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 67 v1.4 tc0_counter=8-bit, tc0x8=1 high speed mode (f osc = 3.58mhz) low speed mode (f osc = 32768hz) tc0rate tc0clock max overflow interval one step = max/256 ma x overflow interval one step = max/256 000 f osc /128 9.153 ms 35.754us 1000 ms 3.91 ms 001 f osc /64 4.58 ms 17.877us 500 ms 1.95 ms 010 f osc /32 2.29 ms 8.939us 250 ms 0.977 ms 011 f osc /16 1.14 ms 4.470us 125 ms 0.488 ms 100 f osc /8 0.57 ms 2.235us 62.5 ms 0.244 ms 101 f osc /4 0.29 ms 1.117us 31.25 ms 0.122 ms 110 f osc /2 0.14 ms 0.587us 15.63 ms 0.061 ms 111 f osc 71.5 us 0.279us 7.81ms 0.03 ms tc0_counter=6-bit, tc0x8=1 high speed mode (f osc = 3.58mhz) low speed mode (f osc = 32768hz) tc0rate tc0clock max overflow interval one step = max/64 ma x overflow interval one step = max/64 000 f osc /128 2.29 ms 35.754us 250 ms 3.91 ms 001 f osc /64 1.14 ms 17.877us 125 ms 1.95 ms 010 f osc /32 0.57 ms 8.939us 62.5 ms 0.977 ms 011 f osc /16 0.29 ms 4.470us 31.25 ms 0.488 ms 100 f osc /8 0.14 ms 2.235us 15.63 ms 0.244 ms 101 f osc /4 71.5 us 1.117us 7.81ms 0.122 ms 110 f osc /2 35.75 us 0.587us 3.905 ms 0.061 ms 111 f osc 17.875 us 0.279us 1.953 ms 0.03 ms tc0_counter=5-bit, tc0x8=1 high speed mode (f osc = 3.58mhz) low speed mode (f osc = 32768hz) tc0rate tc0clock max overflow interval one step = max/32 ma x overflow interval one step = max/32 000 f osc /128 1.14 ms 35.754us 125 ms 3.91 ms 001 f osc /64 0.57 ms 17.877us 62.5 ms 1.95 ms 010 f osc /32 0.29 ms 8.939us 31.25 ms 0.977 ms 011 f osc /16 0.14 ms 4.470us 15.63 ms 0.488 ms 100 f osc /8 71.5 us 2.235us 7.81ms 0.244 ms 101 f osc /4 35.75 us 1.117us 3.905 ms 0.122 ms 110 f osc /2 17.875 us 0.587us 1.953 ms 0.061 ms 111 f osc 8.936 us 0.279us 0.976 ms 0.03 ms tc0_counter=4-bit, tc0x8=1 high speed mode (f osc = 3.58mhz) low speed mode (f osc = 32768hz) tc0rate tc0clock max overflow interval one step = max/16 ma x overflow interval one step = max/16 000 f osc /128 0.57 ms 35.754us 62.5 ms 3.91 ms 001 f osc /64 0.29 ms 17.877us 31.25 ms 1.95 ms 010 f osc /32 0.14 ms 8.939us 15.63 ms 0.977 ms 011 f osc /16 71.5 us 4.470us 7.81ms 0.488 ms 100 f osc /8 35.75 us 2.235us 3.905 ms 0.244 ms 101 f osc /4 17.875 us 1.117us 1.953 ms 0.122 ms 110 f osc /2 8.936 us 0.587us 0.976 ms 0.061 ms 111 f osc 4.468 us 0.279us 0.488 ms 0.03 ms table 8-2. the timing table of timer count tc0
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 68 v1.4 tc0r auto-load register tc0r is an 8-bit register for the tc0 auto-reload function. tc0r?s value applies to tc0out and pwm0out functions. under tc0out application, users must enable and set the tc0r register. the main purpose of tc0r is as following. store the auto-reload value and set into tc 0c when the tc0c overflow. (aload0 = 1). store the duty value of pwm0out function. tc0r initial value = xxxx xxxx 0cdh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0r tc0r7 tc0r6 tc0r5 tc0r4 tc0r3 tc0r2 tc0r1 tc0r0 w w w w w w w w the equation of tc0r initial value is like tc0c as following. tc0r initial value = n - (tc0 interrupt interval time * input clock) which n is determinate by code option: tc0_counter tc0_counter n max. tc0r value 8-bit 256 255 6-bit 64 63 5-bit 32 31 4-bit 16 15 note: thetc0r must small or equal than max. tc0r value. note: the tc0r is write-only register can?t be process by incms, decms instructions.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 69 v1.4 tc0 timer counter operation sequence the tc0 timer counter?s sequence of operation can be following. set the tc0c initial value to setup the interval time. set the tc0enb to be ?1? to enable tc0 timer counter. tc0c is incremented by one with each clock pulse wh ich frequency is corresponding to tc0m selection. tc0c overflows when tc 0c from ffh to 00h. when tc0c overflow occurs, the tc0irq flag is set to be ?1? by hardware. execute the interrupt service routine. users reset the tc0c value and resume the tc0 timer operation. example: setup the tc0m and tc0c withou t auto-reload function.(tc0_counter=8-bit) b0bclr ftc0x8 ; to select tc0=fcpu/2 as clock source b0bclr ftc0ien ; to disable tc0 interrupt service b0bclr ftc0enb ; to disable tc0 timer mov a,#20h ; b0mov tc0m,a ; to set tc0 clock = f cpu / 64 mov a,#74h ; to set tc0c initial value = 74h b0mov tc0c,a ;(to set tc0 interval = 10 ms) b0bset ftc0ien ; to enable tc0 interrupt service b0bclr ftc0irq ; to clear tc0 interrupt request b0bset ftc0enb ; to enable tc0 timer example: setup the tc0m and tc0c with auto-reload function. (tc0_counter=8-bit) b0bclr ftc0x8 ; to select tc0=fcpu/2 as clock source b0bclr ftc0ien ; to disable tc0 interrupt service b0bclr ftc0enb ; to disable tc0 timer mov a,#20h ; b0mov tc0m,a ; to set tc0 clock = f cpu / 64 mov a,#74h ; to set tc0c initial value = 74h b0mov tc0c,a ; (to set tc0 interval = 10 ms) b0mov tc0r,a ; to set tc0r auto-reload register b0bset ftc0ien ; to enable tc0 interrupt service b0bclr ftc0irq ; to clear tc0 interrupt request b0bset ftc0enb ; to enable tc0 timer b0bset aload0 ; to enable tc0 auto-reload function.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 70 v1.4 example: tc0 interrupt service routine without auto-reload function. (tc0_counter=8-bit) org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; store acc value. b0mov a, pflag b0mov pflagbuf, a b0bts1 ftc0irq ; check tc0irq jmp exit_int ; tc0irq = 0, exit interrupt vector b0bclr ftc0irq ; reset tc0irq mov a,#74h ; reload tc0c b0mov tc0c,a . . ; tc0 interrupt service routine . . jmp exit_int ; end of tc0 interrupt service routine and exit interrupt vector . . . . exit_int: b0mov a, pflagbuf b0mov pflag, a b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector example: tc0 interrupt service routine with auto-reload. (tc0_counter=8-bit) org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; store acc value. b0mov a, pflag b0mov pflagbuf, a b0bts1 ftc0irq ; check tc0irq jmp exit_int ; tc0irq = 0, exit interrupt vector b0bclr ftc0irq ; reset tc0irq . . ; tc0 interrupt service routine . . jmp exit_int ; end of tc0 interrupt service routine and exit interrupt vector . . . . exit_int: b0mov a, pflagbuf b0mov pflag, a b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 71 v1.4 tc0 clock frequency output (buzzer) tc0 timer counter provides a frequency output function. by setting the tc0 clock frequency, the clock signal is output to p5.4 and the p5.4 general purpose i/o function is auto-di sable. the tc0 output signal divides by 2. the tc0 clock has many combinations and easily to make difference fr equency. this function applies as buzzer output to output multi-frequency. figure 8-2. the tc0out pulse frequency example: setup tc0out output from tc0 to tc0out (p5.4). the external high-speed clock is 4mhz. the tc0out frequency is 1khz. because the tc0out signal is divided by 2, set the tc0 clock to 2khz. the tc0 clock source is from exte rnal oscillator clock. tc0 rate is f cpu /4. the tc0rate2~tc0rate1 = 110, tc0c = tc0r = 131, tc0x8 = 0, tc0_counter=8-bit b0bclr ftc0x8 ; set tc0x8 to 0 mov a,#01100000b b0mov tc0m,a ; set the tc0 rate to fcpu/4 mov a,#131 ; set the auto-reload reference value b0mov tc0c,a b0mov tc0r,a b0bset ftc0out ; enable tc0 output to p5.4 and disable p5.4 i/o function b0bset faload0 ; enable tc0 auto-reload function b0bset ftc0enb ; enable tc0 timer
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 72 v1.4 tc0out frequency table f osc = 4mhz, tc0 rate = f cpu /8, tc0_counter=8-bit , tc0x8=0 tc0r tc0out (khz) tc0r tc0out (khz) tc0r tc0out (khz) tc0r tc0out (khz) tc0r tc0out (khz) 0 0.2441 56 0.3125 112 0.4340 168 0.7102 224 1.9531 1 0.2451 57 0.3141 113 0.4371 169 0.7184 225 2.0161 2 0.2461 58 0.3157 114 0.4401 170 0.7267 226 2.0833 3 0.2470 59 0.3173 115 0.4433 171 0.7353 227 2.1552 4 0.2480 60 0.3189 116 0.4464 172 0.7440 228 2.2321 5 0.2490 61 0.3205 117 0.4496 173 0.7530 229 2.3148 6 0.2500 62 0.3222 118 0.4529 174 0.7622 230 2.4038 7 0.2510 63 0.3238 119 0.4562 175 0.7716 231 2.5000 8 0.2520 64 0.3255 120 0.4596 176 0.7813 232 2.6042 9 0.2530 65 0.3272 121 0.4630 177 0.7911 233 2.7174 10 0.2541 66 0.3289 122 0.4664 178 0.8013 234 2.8409 11 0.2551 67 0.3307 123 0.4699 179 0.8117 235 2.9762 12 0.2561 68 0.3324 124 0.4735 180 0.8224 236 3.1250 13 0.2572 69 0.3342 125 0.4771 181 0.8333 237 3.2895 14 0.2583 70 0.3360 126 0.4808 182 0.8446 238 3.4722 15 0.2593 71 0.3378 127 0.4845 183 0.8562 239 3.6765 16 0.2604 72 0.3397 128 0.4883 184 0.8681 240 3.9063 17 0.2615 73 0.3415 129 0.4921 185 0.8803 241 4.1667 18 0.2626 74 0.3434 130 0.4960 186 0.8929 242 4.4643 19 0.2637 75 0.3453 131 0.5000 187 0.9058 243 4.8077 20 0.2648 76 0.3472 132 0.5040 188 0.9191 244 5.2083 21 0.2660 77 0.3492 133 0.5081 189 0.9328 245 5.6818 22 0.2671 78 0.3511 134 0.5123 190 0.9470 246 6.2500 23 0.2682 79 0.3531 135 0.5165 191 0.9615 247 6.9444 24 0.2694 80 0.3551 136 0.5208 192 0.9766 248 7.8125 25 0.2706 81 0.3571 137 0.5252 193 0.9921 249 8.9286 26 0.2717 82 0.3592 138 0.5297 194 1.0081 250 10.4167 27 0.2729 83 0.3613 139 0.5342 195 1.0246 251 12.5000 28 0.2741 84 0.3634 140 0.5388 196 1.0417 252 15.6250 29 0.2753 85 0.3655 141 0.5435 197 1.0593 253 20.8333 30 0.2765 86 0.3676 142 0.5482 198 1.0776 254 31.2500 31 0.2778 87 0.3698 143 0.5531 199 1.0965 255 62.5000 32 0.2790 88 0.3720 144 0.5580 200 1.1161 33 0.2803 89 0.3743 145 0.5631 201 1.1364 34 0.2815 90 0.3765 146 0.5682 202 1.1574 35 0.2828 91 0.3788 147 0.5734 203 1.1792 36 0.2841 92 0.3811 148 0.5787 204 1.2019 37 0.2854 93 0.3834 149 0.5841 205 1.2255 38 0.2867 94 0.3858 150 0.5896 206 1.2500 39 0.2880 95 0.3882 151 0.5952 207 1.2755 40 0.2894 96 0.3906 152 0.6010 208 1.3021 41 0.2907 97 0.3931 153 0.6068 209 1.3298 42 0.2921 98 0.3956 154 0.6127 210 1.3587 43 0.2934 99 0.3981 155 0.6188 211 1.3889 44 0.2948 100 0.4006 156 0.6250 212 1.4205 45 0.2962 101 0.4032 157 0.6313 213 1.4535 46 0.2976 102 0.4058 158 0.6378 214 1.4881 47 0.2990 103 0.4085 159 0.6443 215 1.5244 48 0.3005 104 0.4112 160 0.6510 216 1.5625 49 0.3019 105 0.4139 161 0.6579 217 1.6026 50 0.3034 106 0.4167 162 0.6649 218 1.6447 51 0.3049 107 0.4195 163 0.6720 219 1.6892 52 0.3064 108 0.4223 164 0.6793 220 1.7361 53 0.3079 109 0.4252 165 0.6868 221 1.7857 54 0.3094 110 0.4281 166 0.6944 222 1.8382 55 0.3109 111 0.4310 167 0.7022 223 1.8939 table 8-3. tc0out frequency table for f osc = 4mhz, tc0 rate = f cpu /8
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 73 v1.4 f osc = 16mhz, tc0 rate = f cpu /8, tc0_counter=8-bit tc0r tc0out (khz) tc0r tc0out (khz) tc0r tc0out (khz) tc0r tc0out (khz) tc0r tc0out (khz) 0 0.9766 56 1.2500 112 1.7361 168 2.8409 224 7.8125 1 0.9804 57 1.2563 113 1.7483 169 2.8736 225 8.0645 2 0.9843 58 1.2626 114 1.7606 170 2.9070 226 8.3333 3 0.9881 59 1.2690 115 1.7730 171 2.9412 227 8.6207 4 0.9921 60 1.2755 116 1.7857 172 2.9762 228 8.9286 5 0.9960 61 1.2821 117 1.7986 173 3.0120 229 9.2593 6 1.0000 62 1.2887 118 1.8116 174 3.0488 230 9.6154 7 1.0040 63 1.2953 119 1.8248 175 3.0864 231 10.0000 8 1.0081 64 1.3021 120 1.8382 176 3.1250 232 10.4167 9 1.0121 65 1.3089 121 1.8519 177 3.1646 233 10.8696 10 1.0163 66 1.3158 122 1.8657 178 3.2051 234 11.3636 11 1.0204 67 1.3228 123 1.8797 179 3.2468 235 11.9048 12 1.0246 68 1.3298 124 1.8939 180 3.2895 236 12.5000 13 1.0288 69 1.3369 125 1.9084 181 3.3333 237 13.1579 14 1.0331 70 1.3441 126 1.9231 182 3.3784 238 13.8889 15 1.0373 71 1.3514 127 1.9380 183 3.4247 239 14.7059 16 1.0417 72 1.3587 128 1.9531 184 3.4722 240 15.6250 17 1.0460 73 1.3661 129 1.9685 185 3.5211 241 16.6667 18 1.0504 74 1.3736 130 1.9841 186 3.5714 242 17.8571 19 1.0549 75 1.3812 131 2.0000 187 3.6232 243 19.2308 20 1.0593 76 1.3889 132 2.0161 188 3.6765 244 20.8333 21 1.0638 77 1.3966 133 2.0325 189 3.7313 245 22.7273 22 1.0684 78 1.4045 134 2.0492 190 3.7879 246 25.0000 23 1.0730 79 1.4124 135 2.0661 191 3.8462 247 27.7778 24 1.0776 80 1.4205 136 2.0833 192 3.9063 248 31.2500 25 1.0823 81 1.4286 137 2.1008 193 3.9683 249 35.7143 26 1.0870 82 1.4368 138 2.1186 194 4.0323 250 41.6667 27 1.0917 83 1.4451 139 2.1368 195 4.0984 251 50.0000 28 1.0965 84 1.4535 140 2.1552 196 4.1667 252 62.5000 29 1.1013 85 1.4620 141 2.1739 197 4.2373 253 83.3333 30 1.1062 86 1.4706 142 2.1930 198 4.3103 254 125.0000 31 1.1111 87 1.4793 143 2.2124 199 4.3860 255 250.0000 32 1.1161 88 1.4881 144 2.2321 200 4.4643 33 1.1211 89 1.4970 145 2.2523 201 4.5455 34 1.1261 90 1.5060 146 2.2727 202 4.6296 35 1.1312 91 1.5152 147 2.2936 203 4.7170 36 1.1364 92 1.5244 148 2.3148 204 4.8077 37 1.1416 93 1.5337 149 2.3364 205 4.9020 38 1.1468 94 1.5432 150 2.3585 206 5.0000 39 1.1521 95 1.5528 151 2.3810 207 5.1020 40 1.1574 96 1.5625 152 2.4038 208 5.2083 41 1.1628 97 1.5723 153 2.4272 209 5.3191 42 1.1682 98 1.5823 154 2.4510 210 5.4348 43 1.1737 99 1.5924 155 2.4752 211 5.5556 44 1.1792 100 1.6026 156 2.5000 212 5.6818 45 1.1848 101 1.6129 157 2.5253 213 5.8140 46 1.1905 102 1.6234 158 2.5510 214 5.9524 47 1.1962 103 1.6340 159 2.5773 215 6.0976 48 1.2019 104 1.6447 160 2.6042 216 6.2500 49 1.2077 105 1.6556 161 2.6316 217 6.4103 50 1.2136 106 1.6667 162 2.6596 218 6.5789 51 1.2195 107 1.6779 163 2.6882 219 6.7568 52 1.2255 108 1.6892 164 2.7174 220 6.9444 53 1.2315 109 1.7007 165 2.7473 221 7.1429 54 1.2376 110 1.7123 166 2.7778 222 7.3529 55 1.2438 111 1.7241 167 2.8090 223 7.5758 table 8-4. tc0out frequency table for f osc = 16mhz, tc0 rate = fcpu/8
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 74 v1.4 timer counter 1 (tc1) overview the timer counter 1 (tc1) is used to generate an interrupt r equest when a specified time interval has elapsed. tc1 has an auto re-loadable counter that consists of two parts: an 8-bi t reload register (tc1r) into which you write the counter reference value, and an 8-bit counter register (tc1c) whos e value is automatically incremented by counter logic. figure 8-3. timer count tc1 block diagram the main purposes of the tc1 timer is as following. 8-bit programmable timer: generates interrupts at specific time inte rvals based on the selected clock frequency. arbitrary frequency output (buzzer output): outputs selectable clock frequencies to the bz1 pin (p5.3). pwm function: pwm output can be generated by the pwm1out bit and output to pwm1out pin (p5.3). cpum0 tc1r reload data buffer tc1enb tc1c 8-bit binary counter tc1 time out load aload1 auto. reload p5.3 ? 2 tc1out internal p5.3 i/o circuit s r compare pwm1out pwm buzzer 2 (8-tc1rate) f cpu cpum0 tc1r reload data buffer tc1enb tc1c 8-bit binary counter tc1 time out load aload1 auto. reload p5.3 ? 2 tc1out internal p5.3 i/o circuit s r compare pwm1out pwm buzzer 2 (8-tc1rate) f cpu
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 75 v1.4 tc1m mode register the tc1m is the timer mode register, which is an 8-bit read/ write register. by loading different value into the tc1m register, users can modify the timer counter cloc k frequency dynamically when program executing. eight rates for tc1 timer can be selected by tc1rate0 ~ tc1rate2 and tc1x8 bits of t0m register. if tc1x8=1 the tc1 will faster 8 times than tc1x8=0 (initial value). the 7 th bit of tc1m named tc1enb is the control bit to start tc1 timer. tc1m initial value = 0000 0000 0dch bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc1m tc1enb tc1rate2 tc1r ate1 tc1rate0 tc1cks aloa d1 tc1out pwm1out r/w r/w r/w r/w r/w r/w r/w r/w bit7 tc1enb: tc1 counter/bz1/pwm1out enable bit. 0 = disable, 1 = enable. bit [6:4] tc1rate [2:0]: tc1 clock source selection bits. tc1x8 is bit 3 of t0m register. tc1 clock source tc1rate [2:0] tc1x8 = 0 tc1x8 = 1 000 f cpu /256 = f osc /1024 f osc /128 001 f cpu /128 = f osc /512 f osc /64 ? ? ? 110 f cpu /4 = f osc /16 f osc /2 111 f cpu /2 = f osc /8 f osc note: f cpu = f osc / 4 bit3 tc1cks: tc1 clock source select bit. ?0? = f cpu , ?1? = external clock comes fo rm int1/p0.1 pin. tc1 will be an event counter. bit2 aload1: tc1 auto-reload function control bit. 0 = none auto-reload 1 = auto-reload. bit1 tc01ut: tc1 time-out toggle signal output control bit. 0 = to disable tc1 signal output and to enable p5.3?s i/o function, 1 = to enable tc1?s signal output and to disable p5.3?s i/o function. (auto-disable the pwm0out function.) bit0 pwm1out: tc1?s pwm output control bit. 0 = to disable the pwm output, 1 = to enable the pwm output (the tc1out control bit must = 0 ) note: note: when tc1cks=1, tc1 b ecame an external event counter. no more p0.1 interrupt request will be raised. (p01irq will be always 0)
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 76 v1.4 tc1c counting register tc1c is an 8-bit counter register for the timer counter (tc1 ). tc1c must be reset whenever the tc1enb is set ?1? to start the timer. tc0c is incremented by one with a clo ck pulse which the frequency is determined by tc0rate0 ~ tc0rate2. when tc0c has incr emented to ?0ffh?, it is will be cleared to ?00h? in next clock a nd an overflow is generated. under tc1 interrupt service request (tc1ien) enable condition, the tc1 interrupt request flag will be set ?1? and the system executes t he interrupt service routine. tc1c initial value = xxxx xxxx 0ddh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc1c tc1c7 tc1c6 tc1c5 tc1c4 tc1c3 tc1c2 tc1c1 tc1c0 r/w r/w r/w r/w r/w r/w r/w r/w tc1 overflow time tc1 rate is determinate by tc1rate and code option tc 1_counter, tc1rate can set tc1 clock frequency from f cpu and tc1_counter set tc1 became 8-bit, 6-bit, 5-bit or 4-bit counter. the equation of tc1c initial value is as following. tc1c initial value = n - (tc1 interrupt interval time * input clock) which n is determinate by code option: tc1_counter tc1_counter n max. tc1c value 8-bit 256 255 6-bit 64 63 5-bit 32 31 4-bit 16 15 note: thetc1c must small or equal than max. tc1 value. example: to set 10ms interval time for tc1 interrupt at f osc = 3.58mhz. tc1c value (74h) = 256 - (10ms * f cpu /64) (tc1rate=010, tc1_counter=8-bit, tc1x8=0) tc1c initial value = 256 - (tc0 inte rrupt interval time * input clock) = 256 - (10ms * 3.58 * 10 6 / 4 / 64) = 256 - (10 -2 * 3.58 * 10 6 / 4 / 64) = 116 = 74h example: to set 1.25ms interval time for tc1 interrupt at f osc = 3.58mhz. tc1c value (74h) = 256 - (10ms * fcpu/64) (tc1rate=010, tc1_counter=8-bit, tc1x8=1) tc1c initial value = 256 - (tc0 inte rrupt interval time * input clock) = 256 - (1.25ms * 3.58 * 10 6 / 32) = 256 - (0.00125 * 3.58 * 10 6 / 32) = 116 = 74h example: to set 1ms interval time for tc1 interrupt at f osc = 3.58mhz. tc1c value (32h) = 64 - (1ms * f cpu /64) (tc1rate=010, tc1_counter=6-bit, tc1x8=0) tc1c initial value = 64 - (tc0 interrupt interval time * input clock) = 64 - (1ms * 3.58 * 10 6 / 4 / 64) = 64 - (1 -2 * 3.58 * 10 6 / 4 / 64) = 64-14 = 32h
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 77 v1.4 tc1_counter=8-bit, tc1x8=0 high speed mode (f cpu = 3.58mhz / 4) low speed mode (f cpu = 32768hz / 4) tc1rate tc1clock max overflow interval one step = max/256 ma x overflow interval one step = max/256 000 f cpu /256 73.2 ms 286us 8000 ms 31.25 ms 001 f cpu /128 36.6 ms 143us 4000 ms 15.63 ms 010 f cpu /64 18.3 ms 71.5us 2000 ms 7.8 ms 011 f cpu /32 9.15 ms 35.8us 1000 ms 3.9 ms 100 f cpu /16 4.57 ms 17.9us 500 ms 1.95 ms 101 f cpu /8 2.28 ms 8.94us 250 ms 0.98 ms 110 f cpu /4 1.14 ms 4.47us 125 ms 0.49 ms 111 f cpu /2 0.57 ms 2.23us 62.5 ms 0.24 ms tc1_counter=6-bit, tc1x8=0 high speed mode (f cpu = 3.58mhz / 4) low speed mode (f cpu = 32768hz / 4) tc1rate tc1clock max overflow interval one step = max/64 ma x overflow interval one step = max/64 000 f cpu /256 18.3 ms 286us 2000 ms 31.25 ms 001 f cpu /128 9.15 ms 143us 1000 ms 15.63 ms 010 f cpu /64 4.57 ms 71.5us 500 ms 7.8 ms 011 f cpu /32 2.28 ms 35.8us 250 ms 3.9 ms 100 f cpu /16 1.14 ms 17.9us 125 ms 1.95 ms 101 f cpu /8 0.57 ms 8.94us 62.5 ms 0.98 ms 110 f cpu /4 0.285 ms 4.47us 31.25 ms 0.49 ms 111 f cpu /2 0.143 ms 2.23us 15.63 ms 0.24 ms tc1_counter=5-bit, tc1x8=0 high speed mode (f cpu = 3.58mhz / 4) low speed mode (f cpu = 32768hz / 4) tc1rate tc1clock max overflow interval one step = max/32 ma x overflow interval one step = max/32 000 f cpu /256 9.15 ms 286us 1000 ms 31.25 ms 001 f cpu /128 4.57 ms 143us 500 ms 15.63 ms 010 f cpu /64 2.28 ms 71.5us 250 ms 7.8 ms 011 f cpu /32 1.14 ms 35.8us 125 ms 3.9 ms 100 f cpu /16 0.57 ms 17.9us 62.5 ms 1.95 ms 101 f cpu /8 0.285 ms 8.94us 31.25 ms 0.98 ms 110 f cpu /4 0.143 ms 4.47us 15.63 ms 0.49 ms 111 f cpu /2 71.25 us 2.23us 7.81 ms 0.24 ms tc1_counter=4-bit, tc1x8=0 high speed mode (f cpu = 3.58mhz / 4) low speed mode (f cpu = 32768hz / 4) tc1rate tc1clock max overflow interval one step = max/16 ma x overflow interval one step = max/16 000 f cpu /256 4.57 ms 286us 500 ms 31.25 ms 001 f cpu /128 2.28 ms 143us 250 ms 15.63 ms 010 f cpu /64 1.14 ms 71.5us 125 ms 7.8 ms 011 f cpu /32 0.57 ms 35.8us 62.5 ms 3.9 ms 100 f cpu /16 0.285 ms 17.9us 31.25 ms 1.95 ms 101 f cpu /8 0.143 ms 8.94us 15.63 ms 0.98 ms 110 f cpu /4 71.25 us 4.47us 7.81 ms 0.49 ms 111 f cpu /2 35.63 us 2.23us 3.91 ms 0.24 ms
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 78 v1.4 tc1_counter=8-bit, tc1x8=1 high speed mode (f osc = 3.58mhz) low speed mode (f osc = 32768hz) tc1rate tc1clock max overflow interval one step = max/256 ma x overflow interval one step = max/256 000 f osc /128 9.153 ms 35.754us 1000 ms 3.91 ms 001 f osc /64 4.58 ms 17.877us 500 ms 1.95 ms 010 f osc /32 2.29 ms 8.939us 250 ms 0.977 ms 011 f osc /16 1.14 ms 4.470us 125 ms 0.488 ms 100 f osc /8 0.57 ms 2.235us 62.5 ms 0.244 ms 101 f osc /4 0.29 ms 1.117us 31.25 ms 0.122 ms 110 f osc /2 0.14 ms 0.587us 15.63 ms 0.061 ms 111 f osc 71.5 us 0.279us 7.81ms 0.03 ms tc1_counter=6-bit, tc1x8=1 high speed mode (f osc = 3.58mhz) low speed mode (f osc = 32768hz) tc1rate tc1clock max overflow interval one step = max/64 ma x overflow interval one step = max/64 000 f osc /128 2.29 ms 35.754us 250 ms 3.91 ms 001 f osc /64 1.14 ms 17.877us 125 ms 1.95 ms 010 f osc /32 0.57 ms 8.939us 62.5 ms 0.977 ms 011 f osc /16 0.29 ms 4.470us 31.25 ms 0.488 ms 100 f osc /8 0.14 ms 2.235us 15.63 ms 0.244 ms 101 f osc /4 71.5 us 1.117us 7.81ms 0.122 ms 110 f osc /2 35.75 us 0.587us 3.905 ms 0.061 ms 111 f osc 17.875 us 0.279us 1.953 ms 0.03 ms tc1_counter=5-bit, tc1x8=1 high speed mode (f osc = 3.58mhz) low speed mode (f osc = 32768hz) tc1rate tc1clock max overflow interval one step = max/32 ma x overflow interval one step = max/32 000 f osc /128 1.14 ms 35.754us 125 ms 3.91 ms 001 f osc /64 0.57 ms 17.877us 62.5 ms 1.95 ms 010 f osc /32 0.29 ms 8.939us 31.25 ms 0.977 ms 011 f osc /16 0.14 ms 4.470us 15.63 ms 0.488 ms 100 f osc /8 71.5 us 2.235us 7.81ms 0.244 ms 101 f osc /4 35.75 us 1.117us 3.905 ms 0.122 ms 110 f osc /2 17.875 us 0.587us 1.953 ms 0.061 ms 111 f osc 8.936 us 0.279us 0.976 ms 0.03 ms tc1_counter=4-bit, tc1x8=1 high speed mode (f osc = 3.58mhz) low speed mode (f osc = 32768hz) tc1rate tc1clock max overflow interval one step = max/16 ma x overflow interval one step = max/16 000 f osc /128 0.57 ms 35.754us 62.5 ms 3.91 ms 001 f osc /64 0.29 ms 17.877us 31.25 ms 1.95 ms 010 f osc /32 0.14 ms 8.939us 15.63 ms 0.977 ms 011 f osc /16 71.5 us 4.470us 7.81ms 0.488 ms 100 f osc /8 35.75 us 2.235us 3.905 ms 0.244 ms 101 f osc /4 17.875 us 1.117us 1.953 ms 0.122 ms 110 f osc /2 8.936 us 0.587us 0.976 ms 0.061 ms 111 f osc 4.468 us 0.279us 0.488 ms 0.03 ms table 8-5. the timing table of timer count tc1
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 79 v1.4 tc1r auto-load register tc1r is an 8-bit register for the tc1 auto-reload function. tc1r?s value applies to tc1out and pwm1out functions. under tc1out application, users must enable and set the tc1r register. the main purpose of tc1r is as following. store the auto-reload value and set into tc 1c when the tc1c overflow. (aload1 = 1). store the duty value of pwm1out function. tc1r initial value = xxxx xxxx 0deh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc1r tc1r7 tc1r6 tc1r5 tc1r4 tc1r3 tc1r2 tc1r1 tc1r0 w w w w w w w w the equation of tc1r initial value is like tc1c as following. tc1r initial value = n - (tc1 interrupt interval time * input clock) which n is determinate by code option: tc1_counter tc0_counter n max. tc0r value 8-bit 256 255 6-bit 64 63 5-bit 32 31 4-bit 16 15 note: thetc1r must small or equal than max. tc1r value. note: the tc1r is write-only register can?t be process by incms, decms instructions.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 80 v1.4 tc1 timer counter operation sequence the tc1 timer?s sequence of operation can be following. set the tc1c initial value to setup the interval time. set the tc1enb to be ?1? to enable tc1 timer counter. tc1c is incremented by one with each clock pulse wh ich frequency is corresponding to tc1m selection. tc1c overflows if tc1c from ffh to 00h. when tc1c overflow occurs, the tc1irq flag is set to be ?1? by hardware. execute the interrupt service routine. users reset the tc1c value and resume the tc1 timer operation. example: setup the tc1m and tc1c without auto -reload function.(tc1_counter=8-bit, tc1x8=0) b0bclr ftc1x8 ; b0bclr ftc1ien ; to disable tc1 interrupt service b0bclr ftc1enb ; to disable tc1 timer mov a,#20h ; b0mov tc1m,a ; to set tc1 clock = fcpu / 64 mov a,#74h ; to set tc1c initial value = 74h b0mov tc1c,a ;(to set tc1 interval = 10 ms) b0bset ftc1ien ; to enable tc1 interrupt service b0bclr ftc1irq ; to clear tc1 interrupt request b0bset ftc1enb ; to enable tc1 timer example: setup the tc1m and tc1c with auto-r eload function. (tc1_counter=8-bit, tc1x8=0) b0bclr ftc1x8 ; to select tc1=fcpu/2 as clock source b0bclr ftc1ien ; to disable tc1 interrupt service b0bclr ftc1enb ; to disable tc1 timer mov a,#20h ; b0mov tc1m,a ; to set tc1 clock = fcpu / 64 mov a,#74h ; to set tc1c initial value = 74h b0mov tc1c,a ; (to set tc1 interval = 10 ms) b0mov tc1r,a ; to set tc1r auto-reload register b0bset ftc1ien ; to enable tc1 interrupt service b0bclr ftc1irq ; to clear tc1 interrupt request b0bset ftc1enb ; to enable tc1 timer b0bset aload1 ; to enable tc1 auto-reload function.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 81 v1.4 example: tc1 interrupt service routine without au to-reload function. (tc1_counter=8-bit, tc1x8=0) org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; store acc value. b0mov a, pflag b0mov pflagbuf, a b0bts1 ftc1irq ; check tc1irq jmp exit_int ; tc1irq = 0, exit interrupt vector b0bclr ftc1irq ; reset tc1irq mov a,#74h ; reload tc1c b0mov tc1c,a . . ; tc1 interrupt service routine . . jmp exit_int ; end of tc1 interrupt service routine and exit interrupt vector . . . . exit_int: b0mov a, pflagbuf b0mov pflag, a b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector example: tc1 interrupt service routine with auto-reload. (tc1_counter=8-bit, tc1x8=0) org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; store acc value. b0mov a, pflag b0mov pflagbuf, a b0bts1 ftc1irq ; check tc1irq jmp exit_int ; tc1irq = 0, exit interrupt vector b0bclr ftc1irq ; reset tc1irq . . ; tc1 interrupt service routine . . jmp exit_int ; end of tc1 interrupt service routine and exit interrupt vector . . . . exit_int: b0mov a, pflagbuf b0mov pflag, a b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 82 v1.4 tc1 clock frequency output (buzzer) tc1 timer counter provides a frequency output function. by setting the tc1 clock frequency, the clock signal is output to p5.3 and the p5.3 general purpose i/o function is auto-di sable. the tc1 output signal divides by 2. the tc1 clock has many combinations and easily to make difference fr equency. this function applies as buzzer output to output multi-frequency. figure 8-4 tc1out pulse frequency example: setup tc1out output from tc1 to tc1out (p5.3). the external high-speed clock is 4mhz. the tc1out frequency is 1khz. because the tc1out signal is divided by 2, set the tc1 clock to 2khz. the tc1 clock source is from external o scillator clock. tc1 rate is fcpu/ 4. the tc1rate2~tc1rate1 = 110. tc1c = tc1r = 131. tc1_counter=8-bit, tc1x8=0 mov a,#01100000b b0mov tc1m,a ; set the tc1 rate to fcpu/4 mov a,#131 ; set the auto-reload reference value b0mov tc1c,a b0mov tc1r,a b0bset ftc1out ; enable tc1 output to p5.3 and disable p5.3 i/o function b0bset faload1 ; enable tc1 auto-reload function b0bset ftc1enb ; enable tc1 timer
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 83 v1.4 pwm function description overview pwm function is generated by tc0/tc1 timer counter and output the pwm signal to pwm0out pin (p5.4)/ pwm1out pin (p5.3). when code option tc0/tc1_counter= 8- bit, the counter counts modulus 256, from 0-255, inclusive. the value of the 8-bit counter is compared to t he contents of the reference r egister (tc0r/tc1r). when the reference register value (tc0r/tc1r) is equal to the counter value (tc0c/tc1c), the pwm output goes low. when the counter reaches zero, the pwm output is forced high. table 7-4 listed the low-to-high ratio (duty) of the pwm0/pwm1 output. for example, tc0_counter=8-bit, all pwm outputs remain inac tive during the first 256 input clock signals. then, when the counter value (tc0c/tc1c) changes from ffh back to 00h , the pwm output is forced to high level. the pulse width ratio (duty cycle) is defined by the contents of the reference regist er (tc0r/tc1r) and is programmed in increments of 1:256. the 8-bit pwm data register tc0r /tc1r is write-only register. different code option of tc0_counter/tc1_counter will cause different pwm duty, so user can generate different pwm output by selection different tc0_counter/tc1_counter. pwm output can be held at low level by continuously loading the reference register with 00h. under pwm operating, to change the pwm?s duty cycle is to modify the tc0r/tc1r. tc0x8/tc1x8 pwm0 frequency pwm1 frequency 0 f osc /(2 10-tc0rate )/n f osc /(2 10-tc1rate )/n 1 f osc /(2 7-tc0rate ) /n f osc /(2 7-tc1rate ) /n the value of n depend on code option tc0_counter/tc1_counter tc0_counter/tc1_counter n pwm duty cycle 8-bit 256 0/256 ~ 255/256 6-bit 64 0/64 ~ 63/64 5-bit 32 0/32 ~ 31/32 4-bit 16 0/16 ~ 15/16 table 8-1. the pwm frequency calculation formula tc0x8 tc1x8 tc0_counter tc1_counter tc0/tc1 overflow boundary pwm duty cycle max pwm frequency (f osc = 4mhz) note 0 8-bit ffh to 00h 0/256 ~ 255/256 1.953125k overflow per 256 count 0 6-bit 3fh to 40h 0/64 ~ 63/64 7.8125k overflow per 64 count 0 5-bit 1fh to 20h 0/32 ~ 31/32 15.625k overflow per 32 count 0 4-bit 0fh to 10h 0/16 ~ 15/16 31.25k overflow per 16 count 1 8-bit ffh to 00h 0/256 ~ 255/256 15.625 overflow per 256 count 1 6-bit 3fh to 40h 0/64 ~ 63/64 62.5k overflow per 64 count 1 5-bit 1fh to 20h 0/32 ~ 31/32 125k overflow per 32 count 1 4-bit 0fh to 10h 0/16 ~ 15/16 250k overflow per 16 count table 8-2. the maximum pwm frequenc y example (tc0rate/tc1rate = 111)
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 84 v1.4 reference register value (tc0r/tc1r) tc0/1_counter=8-bit duty cycle tc0/1_counter=6-bit duty cycle tc0/1_counter=5-bit duty cycle tc0/1_counter=4-bit duty cycle 0000 0000 0/256 0/64 0/32 0/16 0000 0001 1/256 1/64 1/32 1/16 0000 0010 2/256 2/64 2/32 2/16 ? ? ? ? ? 0000 1110 14/256 14/64 14/32 14/16 0000 1111 15/256 15/64 15/32 15/16 0001 0000 16/256. 16/64 16/32 n/a ? ? ? ? n/a 0001 1110 30/256 30/64 30/32 n/a 0001 1111 31/256 31/64 31/32 n/a 0010 0000 32/256. 32/64 n/a n/a ? ? ? n/a n/a 0011 1110 62/256 62/64 n/a n/a 0011 1111 63/256 63/64 n/a n/a 0100 0000 64/256. n/a n/a n/a ? ? n/a n/a n/a 1111 1110 254/256 n/a n/a n/a 1111 1111 255/256 n/a n/a n/a table 8-3. the pwm duty cycle table note: functionality is not guaranteed in shaded area.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 85 v1.4 figure 8-5 the output of pwm with different tc0r/tc1r. (tc0/tc1_counter=8-bit) figure 8-6 the output of pwm with different tc0_count tc0/tc1 clock tc0r/tc1r = 00h low high low low high tc0r/tc1r = 01h tc0r/tc1r = 80h tc0r/tc1r = ffh low high 01 128 ..... 254 255 ..... 01 128 ..... 254 255 ..... tc0/tc1 clock tc0r/tc1r = 00h low high low low high tc0r/tc1r = 01h tc0r/tc1r = 80h tc0r/tc1r = ffh low high low high 01 128 ..... 254 255 ..... 01 128 ..... 254 255 ..... 01 128 ..... 254 255 ..... ..... 01 128 ..... 254 255 ..... ..... 0 tc0 clock tc0r = 01h tc0_count:4-bit high low tc0r = 01h tc0_count:5-bit high low tc0r = 01h tc0_count:6-bit high low tc0r = 01h tc0_count:8-bit high low ... 1 2 16 ... 17 18 32 ... 33 34 64 ... 65 66 255 ... 01 0 tc0 clock tc0r = 01h tc0_count:4-bit high low tc0r = 01h tc0_count:5-bit high low tc0r = 01h tc0_count:6-bit high low tc0r = 01h tc0_count:8-bit high low ... 1 2 16 ... 17 18 32 ... 33 34 64 ... 65 66 255 ... 01
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 86 v1.4 pwm program description example: setup pwm0 output from tc0 to pwm0out (p5.4). the extern al high-speed oscillator clock is 4mhz. the duty of pwm is 30/256. the pwm frequenc y is about 1khz. the pwm clock source is from external oscillator clock. tc0 rate is fcpu/4. the tc0rate2~tc0rate1 = 110, tc 0c = tc0r = 30, tc0x8 =0, tc0_counter=8-bit b0bclr ftc0x8 ; mov a,#01100000b b0mov tc0m,a ; set the tc0 rate to fcpu/4 mov a,#0x00 ;first time initial tc0 b0mov tc0c,a mov a,#30 ; set the pwm duty to 30/256 b0mov tc0r,a b0bclr ftc0out ; dis able tc0out function. b0bset fpwm0out ; enable pwm0 output to p5.4 and disable p5.4 i/o function b0bset ftc0enb ; enable tc0 timer note1: the tc0r and tc1r are write-only registers. don?t process them using incms, decms instructions. note2: set tc0c at initial is to make first duty-cycle correct. after tc0 is enabled, don?t modify tc0r value to avoid duty cycle error of pwm output. example: modify tc0r/tc1r registers? value. mov a, #30h ; input a number using b0mov instruction. b0mov tc0r, a incms buf0 ; get the new tc0r value from the buf0 buffer defined by b0mov a, buf0 ; programming. b0mov tc0r, a note2: that is better to set the tc0c and tc0r value together when pwm0 duty modified. it protects the pwm0 signal no glitch as pwm0 duty changing. that is better to set the tc1c and tc1r value together when pwm1 duty modified. it protects the pwm1 signal no glitch as pwm1 duty changing. note3: the tc0out function must be set ?0? when pwm0 output enable. the tc1out function must be set ?0? when pwm1 output enable. note4: the pwm can work with interrupt request.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 87 v1.4 9 9 9 interrupt overview the sn8p1900 provides 6 interrupt sources, including four internal interrupts (t0, tc0, tc1 & sio) and two external interrupts (int0 ~ int1). these external interrupts can wakeup the chip from power down mode to high-speed normal mode. the external clock input pins of int0/int1 are shared with p0.0/p0.1 pins. once interrupt service is executed, the gie bit in stkp register will clear to ?0? for stopping ot her interrupt request. when inte rrupt service exits, the gie bit will set to ?1? to accept the next inte rrupts? request. all of the interrupt request si gnals are stored in intrq register. the user can program the chip to check intr q?s content for setting executive priority. intrq 6-bit latches t0irq tc0irq tc1irq p00irq interrupt enable gating global interrupt request signal interrupt vector address (0008h) t0 time out tc0 time out tc1 time out inten interrupt enable register int0 trigger the interrupt trigger edge : int0 ~ int1 = falling edge p01irq int1 trigger sioirq sio time out figure 9-1. the 6 interrupts of sn8p1900 note: the gie bit must enable a nd all interrupt operations work.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 88 v1.4 inten interrupt enable register inten is the interrupt request control register including fo ur internal interrupts, three external interrupts and sio interrupt enable control bits. one of the register to be set ?1? is to enable the interrupt request function. once of the interrupt occur, the program jump to org 8 to execute in terrupt service routines. the program exits the interrupt service routine when the returning interrupt serv ice routine instruction (reti) is executed. inten initial value = x000 0000 0c9h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 inten 0 tc1ien tc0ien t0ien sioien 0 p01ien p00ien - r/w r/w r/w r/w - r/w r/w p00ien : external p0.0 interrupt control bit. 0 = disable, 1 = enable. p01ien : external p0.1 interrupt control bit. 0 = disable, 1 = enable. sioien : sio interrupt control bit. 0 = disable, 1 = enable. t0ien : t0 timer interrupt control bit. 0 = disable, 1 = enable. tc0ien : timer 0 interrupt control bit. 0 = disable, 1 = enable. tc1ien : timer 1 interrupt control bit. 0 = disable, 1 = enable. intrq interrupt request register intrq is the interrupt request flag regist er. the register includes all interrupt request indication flags. each one of these interrupt request occurs, the bit of the intrq register would be set ?1?. the intrq value needs to be clear by programming after detecting the flag. in the interrupt vect or of program, users know the any interrupt requests occurring by the register and do the routi ne corresponding of the interrupt request. intrq initial value = x000 0000 0c8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 intrq 0 tc1irq tc0irq t0irq sioirq 0 p01irq p00irq - r/w r/w r/w r/w - r/w r/w bit0 p00irq: external p0.0 interrupt request bit. 0 = non-request 1 = request. bit1 p01irq: external p0.1 interrupt request bit. 0 = non-request 1 = request. bit3 sioirq: sio interrupt request bit. 0 = non-request 1 = request. bit4 t0irq: t0 timer interrupt request bit. 0 = non-request 1 = request. bit5 tc0irq: tc0 timer interrupt request controls bit. 0 = non request 1 = request. bit6 tc1irq: tc1 timer interrupt request controls bit. 0 = non request 1 = request. when interrupt occurs, the related request bit of intrq r egister will be set to ?1? no matter the related enable bit of inten register is enabled or disabled. if the related bit of in ten = 1 and the related bit of intrq is also set to be ?1?. as the result, the system will execute the interrupt vector (org 8). if the re lated bit of inten = 0, moreover, the system won?t execute interrupt vector even when the related bit of intrq is set to be ?1?. users need to be cautious with the operation under multi-interrupt situation.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 89 v1.4 interrupt operation description sn8p1900 provides 6 interrupts. the operatio n of the 6 interrupts is as following. gie global interrupt operation gie is the global interrupt control bit. all interrupts start work after the gie = 1. it is necessary for interrupt service request. one of the interrupt requests occurs, and the program co unter (pc) points to the interrupt vector (org 8) and the stack add 1 level. stkp initial value = 0xxx 1111 0dfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stkp gie - - - stkpb3 stkpb2 stkpb1 stkpb0 r/w - - - r/w r/w r/w r/w gie: global interrupt control bit. 0 = disable 1 = enable. example: set global interrupt control bit (gie). b0bset fgie ; enable gie note: the gie bit must enable a nd all interrupt operations work.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 90 v1.4 int0 (p0.0) interrupt operation the p0.0 interrupt trigger direction is control by pedge register. pedge initial value = 0xx0 0xxx 0bfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pedge pedgen - - p00g1 p00g0 - - - r/w - - r/w r/w - - - bit7 pedgen: interrupt and wakeup trigger edge control bit. 0 = disable edge trigger function. port 0: low-level wakeup trigger and falling edge interrupt trigger. port 1: low-level wakeup trigger. 1 = enable edge trigger function. p0.0: both wakeup and interrupt trigger are controlled by p00g1 and p00g0 bits. p0.1: both wakeup and interrupt trigger are level change (falling or rising edge). port 1: wakeup trigger is level change (falling or rising edge). bit[4:3] p00g[1:0]: port 0.0 edge select bits. 00 = reserved, 01 = falling edge, 10 = rising edge, 11 = rising/falling bi-direction. example: int0 interrupt request setup. b0bset fp00ien ; enable int0 interrupt service b0bclr fp00irq ; clear int0 interrupt request flag b0bset fgie ; enable gie example: int0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; store acc value. push ; push b0bts1 fp00irq ; check p00irq jmp exit_int ; p00irq = 0, exit interrupt vector b0bclr fp00irq ; reset p00irq . . ; int0 interrupt service routine . . exit_int: pop ; pop b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector when the int0 trigger occurs, the p00irq will be set to ?1 ? no matter the p00ien is enable or disable. if the p00ien = 1 and the trigger event p00irq is also set to be ?1?. as t he result, the system will execute the interrupt vector (org 8). if the p00ien = 0 and the trigger event p00irq is still se t to be ?1?. moreover, the sy stem won?t execute interrupt vector even when the p00irq is set to be ?1?. users need to be cautious with the operation under multi-interrupt situation.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 91 v1.4 int1 (p0.1) interrupt operation the int1 is triggered by falling edge. when the int1 trigge r occurs, the p01irq will be set to ?1? however the p01ien is enable or disable. if the p01ien = 1, the trigger event will make the p01irq to be ?1? and the system enter interrupt vector. if the p01ien = 0, the trigger ev ent will make the p01irq to be ?1? but t he system will not enter interrupt vector. users need to care for the operation under multi-interrupt situation. example: int1 interrupt request setup. b0bset fp01ien ; enable int1 interrupt service b0bclr fp01irq ; clear int1 interrupt request flag b0bset fgie ; enable gie example: int1 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; store acc value. push ; push b0bts1 fp01irq ; check p01irq jmp exit_int ; p01irq = 0, exit interrupt vector b0bclr fp01irq ; reset p01irq . . ; int1 interrupt service routine . . exit_int: pop ; pop b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 92 v1.4 t0 interrupt operation when the t0c counter occurs overflow, the t0irq will be se t to ?1? however the t0ien is enable or disable. if the t0ien = 1, the trigger event will make the t0irq to be ?1? a nd the system enter interrupt ve ctor. if the t0ien = 0, the trigger event will make the t0irq to be ?1? but the system will not enter interr upt vector. users need to care for the operation under multi-interrupt situation. example: t0 interrupt request setup. b0bclr ft0ien ; disable t0 interrupt service b0bclr ft0enb ; disable t0 timer mov a, #20h ; b0mov t0m, a ; set t0 clock = f cpu / 64 mov a, #74h ; set t0c initial value = 74h b0mov t0c, a ; set t0 interval = 10 ms b0bset ft0ien ; enable t0 interrupt service b0bclr ft0irq ; clear t0 interrupt request flag b0bset ft0enb ; enable t0 timer b0bset fgie ; enable gie example: t0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; store acc value. push ; push b0bts1 ft0irq ; check t0irq jmp exit_int ; t0irq = 0, exit interrupt vector b0bclr ft0irq ; reset t0irq mov a, #74h b0mov t0c, a ; reset t0c. . . ; t0 interrupt service routine . . exit_int: pop ; pop b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 93 v1.4 tc0 interrupt operation when the tc0c counter occurs overflow, the tc0irq will be se t to ?1? however the tc0ien is enable or disable. if the tc0ien = 1, the trigger event will make the tc0irq to be ?1? and the system enter interrupt vector. if the tc0ien = 0, the trigger event will make the tc0irq to be ?1? but the sy stem will not enter interrupt vector. users need to care for the operation under multi-interrupt situation. example: tc0 interrupt request setup. b0bclr ftc0ien ; disable tc0 interrupt service b0bclr ftc0enb ; disable tc0 timer mov a, #20h ; b0mov tc0m, a ; set tc0 clock = f cpu / 64 mov a, #74h ; set tc0c initial value = 74h b0mov tc0c, a ; set tc0 interval = 10 ms b0bset ftc0ien ; enable tc0 interrupt service b0bclr ftc0irq ; clear tc0 interrupt request flag b0bset ftc0enb ; enable tc0 timer b0bset fgie ; enable gie example: tc0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; store acc value. push ; push b0bts1 ftc0irq ; check tc0irq jmp exit_int ; tc0irq = 0, exit interrupt vector b0bclr ftc0irq ; reset tc0irq mov a, #74h b0mov tc0c, a ; reset tc0c. . . ; tc0 interrupt service routine . . exit_int: pop ; pop b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 94 v1.4 tc1 interrupt operation when the tc1c counter occurs overflow, the tc1irq will be se t to ?1? however the tc1ien is enable or disable. if the tc1ien = 1, the trigger event will make the tc1irq to be ?1? and the system enter interrupt vector. if the tc1ien = 0, the trigger event will make the tc1irq to be ?1? but the sy stem will not enter interrupt vector. users need to care for the operation under multi-interrupt situation. example: tc1 interrupt request setup. b0bclr ftc1ien ; disable tc1 interrupt service b0bclr ft c1enb ; disable tc1 timer mov a, #20h ; b0mov tc1m, a ; set tc1 clock = f cpu / 64 mov a, #74h ; set tc1c initial value = 74h b0mov tc1c, a ; set tc1 interval = 10 ms b0bset ftc1ien ; enable tc1 interrupt service b0bclr ftc1irq ; clear tc1 interrupt request flag b0bset ftc1enb ; enable tc1 timer b0bset fgie ; enable gie example: tc1 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; store acc value. push ; push b0bts1 ftc1irq ; check tc1irq jmp exit_int ; tc1irq = 0, exit interrupt vector b0bclr ftc1irq ; reset tc1irq mov a, #74h b0mov tc1c, a ; reset tc1c. . . ; tc1 interrupt service routine . . exit_int: pop ; pop b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 95 v1.4 sio interrupt operation when the sio finished transmitting, the sioirq will be set to ?1? however the sioien is enable or disable. if the sioien = 1, the trigger event will make the sioirq to be ?1? and the system enter interrupt vector. if the sioien = 0, the trigger event will make the sioirq to be ?1? but the syst em will not enter interrupt ve ctor. users need to care for the operation under multi-interrupt situation. example: sio interrupt request setup. b0bset fsioien ; enable sio interrupt service b0bclr fsioirq ; clear sio interrupt request flag b0bset fgie ; enable gie example: sio interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; store acc value. push ; push b0bts1 fsioirq ; check sioirq jmp exit_int ; sioirq = 0, exit interrupt vector b0bclr fsioirq ; reset sioirq . . ; sio interrupt service routine . . exit_int: pop ; pop b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 96 v1.4 multi-interrupt operation in most conditions, the software designer uses more t han one interrupt request. processing multi-interrupt request needs to set the priority of these interrupt requests. the ir q flags of the 6 interrupts ar e controlled by the interrupt event occurring. set irq flag to 1 doesn?t mean the system to execute the interrupt vector. the irq flags can be triggered by the events without interrupt enable. just only any the event occurs and the ir q will be logic ?1?. the irq and its trigger event relationship is as the below table. interrupt name trigger event description p00irq p0.0 trigger controlled by pedge p01irq p0.1 trigger. falling edge. t0irq t0c overflow. tc0irq tc0c overflow. tc1irq tc1c overflow. sioirq end of sio transmitter operating. there are two things need to do for multi-interrupt. one is to make a good priority for these interrupt requests. two is using ien and irq flags to decide executing interrupt servic e routine or not. users have to check interrupt control bit and interrupt request flag in interrupt vector. there is a simple routine as following.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 97 v1.4 example: how does users check the interrupt request in multi-interrupt situation? org 8 ; interrupt vector b0xch a, accbuf ; store acc value. push ; push intp00chk: ; check int0 interrupt request b0bts1 fp00ien ; check p00ien jmp intp01chk ; jump check to next interrupt b0bts0 fp00irq ; check p00irq jmp intp00 ; jump to int0 interrupt service routine intp01chk: ; check int1 interrupt request b0bts1 fp01ien ; check p01ien jmp intp02chk ; jump check to next interrupt b0bts0 fp01irq ; check p01irq jmp intp01 ; jump to int1 interrupt service routine intt0chk: ; check t0 interrupt request b0bts1 ft0ien ; check t0ien jmp inttc0chk ; jump check to next interrupt b0bts0 ft0irq ; check t0irq jmp intt0 ; jump to t0 interrupt service routine inttc0chk: ; check tc0 interrupt request b0bts1 ftc0ien ; check tc0ien jmp inttc1chk ; jump check to next interrupt b0bts0 ftc0irq ; check tc0irq jmp inttc0 ; jump to tc0 interrupt service routine inttc1hk: ; check tc1 interrupt request b0bts1 ftc1ien ; check tc1ien jmp intsiochk ; jump check to next interrupt b0bts0 ftc1irq ; check tc1irq jmp inttc1 ; jump to tc1 interrupt service routine intsiochk: ; check sio interrupt request b0bts1 fsioien ; check sioien jmp int_exit ; jump to exit of irq b0bts0 fsioirq ; check sioirq jmp intsio ; jump to sio interrupt service routine int_exit: pop ; pop b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 98 v1.4 1 1 1 0 0 0 serial input/output transceiver (sio) overview the sio (serial input/output) transceiver allows high-speed synchronous data transfer between this chip and peripheral devices or between several mcu. these peripheral devices may be serial eeproms, shift registers, display drivers, etc. the sn8p2700a sio featur es include the following: full-duplex, 3-wire synchronous data transfer tx/rx or tx only mode master (sck is clock output) or sl ave (sck is clock input) operation lsb first data transfer two programmable bit rates (only in master mode) end-of-transfer interrupt the siom register can control sio operating function, such as: transmit/receive, clock rate, transfer edge and starting this circuit. this sio circuit will tran smit or receive 8-bit data automatically by setting senb and start bits in siom register. the siob is an 8-bit buffer, which is design ed to store transfer data. sioc and sior are designed to generate sio?s clock source with auto-reload function. the 3-bit i/o counter can monitor the operation of sio and announce an interrupt request after transmitting/receiving 8- bit data. after transferring 8-bit data, this circuit will be disabled automatically and re-transfer data by programming siom register. siob 8-bit buffer senb, txrx so/p5.2 pin siom register sck/p5.0 pin senb si/p5.1 pin sio time out 3-bit i/o counter sckmd senb senb auto_reload sioc 8-bit binary counter sior register senb srate sckmd sedge data bus reset sck sources cpum1,0 cpum1,0 cpum1,0 siob 8-bit buffer senb, txrx so/p5.2 pin siom register sck/p5.0 pin senb si/p5.1 pin sio time out 3-bit i/o counter sckmd senb senb auto_reload sioc 8-bit binary counter sior register senb srate sckmd sedge data bus reset sck sources cpum1,0 cpum1,0 cpum1,0 figure 10-1. sio interface circuit diagram
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 99 v1.4 following figure shows a typical transfer between two micr o-controllers. process 1 sends sck for initial the data transfer. when both processors must work in the same cl ock edge, both controllers woul d send and receive data at the same time. figure 10-2. sio data transfer diagram figure 10-3. sio data timing chart msb lsb msb lsb process 1 process 2 sck sck sio clock sdo sdo sdi sdi siob 8 bit buffer siob 8 bit buffer siom register siom register msb lsb msb lsb process 1 process 2 sck sck sio clock sdo sdo sdi sdi siob 8 bit buffer siob 8 bit buffer siom register siom register shift data in shift data out bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 si (p5.1) bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 so (p5.2) (tx/rx = 1) shift data in general purpose i/o pin so (p5.2) (tx/rx = 0) bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 si (p5.1) sck (p5.0) (tx/rx = 0, sedge = 1) sck (p5.0) (tx/rx = 0, sedge = 0) sck (p5.0) (tx/rx = 1, sedge = 0) sck (p5.0) (tx/rx = 1, sedge = 1)
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 100 v1.4 siom mode register siom initial value = 0000 x000 0b4h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 siom senb start srate1 srate0 sig sckmd sedge txrx r/w r/w r/w r/w r/w r/w r/w r/w senb: sio function control bit. 0 = disable (p5.0~p5.2 is general purpose port) 1 = enable (p5.0~p5.2 is sio pins). start: sio progress control bit. 0 = end of transmit 1 = progressing. srate [1:0] : sio transmit rate select bit. 00 = f cpu , 01 = f cpu /32, 10 = f cpu /16, 11 = f cpu /8. (note: these 2-bits are workless when sckmd=1) sig: start sio receiver function automatically. 0 = disable 1 = enable. sckmd: sio clock mode select bit. 0 = internal 1 = external mode. sedge: sio transmit clock edge select bit. 0 = falling edge 1 = raising edge txrx: sio transfer direction select bit. 0 = receive only 1 = transmit/receive full duplex. note 1: if sckmd=1 for external clock, the sio is in slave mode. if sckmd=0 for internal clock, the sio is in master mode. note 2: don?t set senb and start bits in th e same time. that makes the sio function error.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 101 v1.4 because sio function is shared with port5 for p5.0 as sck, p5.1 as si and p5.2 as so the following table showed the port5[2:0] i/o mode behavior and setting when sio function enable and disable senb=1 (sio function enable) (sckmd=1) sio source = external clock p5.0 will change to input mode automatically, no matter what p5m setting p5.0/sck (sckmd=0) sio source = internal clock p5.0 will change to output mode automatically, no matter what p5m setting p5.1/si p5.1 must be set as input mode in p5m, or the sio function will be abnormal (txrx=1) sio = transmitter/receiver p5.2 will change to output mode automatically, no matter what p5m setting p5.2/so (txrx=0) sio = receiver only p5.2 will change to input mode automatically, no matter what p5m setting senb=0 (sio function disable) p5.0/p5.1/p5.2 port5 [2:0] i/o mode are fully controlled by p5m when sio function disable siob data buffer siob initial value = 0000 0000 0b6h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 siob siob7 siob6 siob5 siob4 siob3 siob2 siob1 siob0 r/w r/w r/w r/w r/w r/w r/w r/w siob is the sio data buffer register. it stores serial i/o transmit and receive data. sior register description sior initial value = 0000 0000 0b5h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sior sior7 sior6 sior5 sior4 sior3 sior2 sior1 sior0 w w w w w w w w the sior is designed for the sio counter to reload the count ed value when end of counting. it is like a post-scalar of sio clock source and let sio has more flexible to setti ng sck range. users can set the sior value to setup sio transfer time. to setup sior value equation to desire transfer time is as following. sck frequency = sio rate / (256 - sior) sior = 256 - ( 1 / ( sck frequency ) * sio rate ) example: setup the sio clock to be 5khz. f osc = 3.58mhz. sio rate = f cpu = f osc /4. sior = 256 ? (1/(5khz) * 3.58mhz/4) = 256 ? (0.0002*895000) = 256 ? 179 = 77
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 102 v1.4 sio master operating description under master-transmitter situation, the sck has two directions as following. sck sck figure 10-4. the two sck directions of sio master operation rising edge transmitter/receiver mode example: master tx/rx rising edge mov a,txdata ; load transmitted data into siob register. b0mov siob,a mov a,#0ffh ; set sio clock with auto-reload function. b0mov sior,a mov a,#10000011b ; setup siom and enable sio function. rising edge. b0mov siom,a b0bset fstart ; start trans fer and receiving sio data. chk_end: b0bts0 fstart ; wait the end of sio operation. jmp chk_end b0mov a,siob ; save siob data into rxdata buffer. mov rxdata,a so di4 do2 di3 di7 do6 di0 do1 do4 do5 di5 si tx/rx data di2 lsb msb do0 do7 sck do3 di6 di1 figure 10-5. the rising edge timing diagram of master transmit and receive operation
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 103 v1.4 falling edge transmitter/receiver mode example: master tx/rx falling edge mov a,txdata ; load transmitted data into siob register. b0mov siob,a mov a,#0ffh ; set sio clock with auto-reload function. b0mov sior,a mov a,#10000001b ; setup siom and enable sio function. falling edge. b0mov siom,a b0bset fstart ; start trans fer and receiving sio data. chk_end: b0bts0 fstart ; wait the end of sio operation. jmp chk_end b0mov a,siob ; save siob data into rxdata buffer. mov rxdata,a do2 sck do1 tx/rx data do0 di7 di6 di5 di4 si di3 do7 di2 do6 so di1 do5 di0 msb do4 lsb do3 figure 10-6. the falling edge timing diagram of master transmit and receive operation
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 104 v1.4 rising edge receiver mode example: master rx rising edge mov a,#0ffh ; set sio clock with auto-reload function. b0mov sior,a mov a,#10000010b ; setup siom and enable sio function. rising edge. b0mov siom,a b0bset fstart ; start receiving sio data. chk_end: b0bts0 fstart ; wait the end of sio operation. jmp chk_end b0mov a,siob ; save siob data into rxdata buffer. mov rxdata,a di0 di7 di6 so di5 normal i/o application di4 sck rx data di3 lsb di2 di1 msb si figure 10-7. the rising edge timing diag ram of master receiving operation
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 105 v1.4 falling edge receiver mode example: master rx falling edge mov a,#0ffh ; set sio clock with auto-reload function. b0mov sior,a mov a,#10000000b ; setup siom and enable sio function. falling edge. b0mov siom,a b0bset fstart ; start receiving sio data. chk_end: b0bts0 fstart ; wait the end of sio operation. jmp chk_end b0mov a,siob ; save siob data into rxdata buffer. mov rxdata,a so si di0 rx data lsb normal i/o application di7 di6 di5 di4 msb di3 di2 di1 sck figure 10-8. the falling edge timing diag ram of master receiving operation
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 106 v1.4 sio slave operating description under slave-receiver situation, the sck has four phases as following. sck4 sck3 sck2 sck1 figure 10-9. the four phases of sck clock when sio is slave operation.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 107 v1.4 rising edge transmitter/receiver mode example: slave tx/rx rising edge mov a,txdata ; load transfer data into siob register. b0mov siob,a mov a,# 10000111b ; setup siom and enable sio function. rising edge. b0mov siom,a b0bset fstart ; start trans fer and receiving sio data. chk_end: b0bts0 fstart ; wait the end of sio operation. jmp chk_end b0mov a,siob ; save siob data into rxdata buffer. mov rxdata,a di0 do6 do1 di5 di4 do7 si di1 do2 di7 di2 sck1 msb do0 di6 so lsb do4 tx/rx data di3 do3 do5 di7 do0 do4 msb do5 di4 di5 do2 so di6 do3 tx/rx data lsb di2 sck2 do6 di1 di3 di0 do1 si do7 figure 10-10. the rising edge timing diagram of slave transfer and receiving operation
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 108 v1.4 falling edge transmitter/receiver mode example: slave tx/rx falling edge mov a,txdata ; load transfer data into siob register. b0mov siob,a mov a,# 10000101b ; setup siom and enable sio function. falling edge. b0mov siom,a b0bset fstart ; start trans fer and receiving sio data. chk_end: b0bts0 fstart ; wait the end of sio operation. jmp chk_end b0mov a,siob ; save siob data into rxdata buffer. mov rxdata,a do7 do6 do5 msb so do4 lsb do1 do3 do2 sck3 do0 di7 di6 di5 di4 di3 di2 di1 si di0 tx/rx data si do2 lsb do1 do0 di7 so di6 di5 msb di4 di3 sck4 do7 tx/rx data do6 di2 do5 di1 di0 do4 do3 figure 10-11. the falling edge timing diagram of slave transfer and receiving operation
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 109 v1.4 rising edge receiver mode example: slave rx rising edge mov a,# 10000110b ; setup siom and enable sio function. rising edge. b0mov siom,a b0bset fstart ; start receiving sio data. chk_end: b0bts0 fstart ; wait the end of sio operation. jmp chk_end b0mov a,siob ; save siob data into rxdata buffer. mov rxdata,a lsb di6 msb rx data sck3 so si di5 di0 di4 normal i/o application di2 di3 di1 di7 normal i/o application lsb msb so rx data sck4 di3 di2 di7 di6 si di5 di0 di4 di1 figure 10-12. the rising edge timing diagram of slave receiving operation
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 110 v1.4 falling edge receiver mode example: slave rx falling edge mov a,# 10000100b ; setup siom and enable sio function. falling edge. b0mov siom,a b0bset fstart ; start receiving sio data. chk_end: b0bts0 fstart ; wait the end of sio operation. jmp chk_end b0mov a,siob ; save siob data into rxdata buffer. mov rxdata,a di5 di4 rx data di3 di7 di2 di1 normal i/o application di0 si lsb sck1 so msb di6 di1 si di0 rx data sck2 so msb di7 lsb di6 normal i/o application di5 di4 di3 di2 figure 10-13. the falling edge timing diagram of slave receiving operation
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 111 v1.4 sio interrupt operation description the sio provides an interrupt function. us ers can process sio data after the sio interrupt request occurring. there is an example for the application as following. example: sio interrupt demo routine. main: mov a,# 10000100b ; setup siom and enable sio function. falling edge. b0mov siom,a b0bset fstart ; start transfer sio data. . . . . jmp main org 8 ; interrupt vector b0xch a, accbuf push b0bts1 fsioirq jmp int_exit b0mov a,siob ; save siob data into rxdata buffer. mov rxdata,a b0bclr fsioirq ; clear si o interrupt request flag. int_exit: pop b0xch a, accbuf
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 112 v1.4 1 1 1 1 1 1 i/o port overview the sn8p1900 provides up to four ports fo r users? application, consisting of two i nput only ports (p0, p2), two i/o ports (p1, p5). the direction of i/o port is selected by p n m register. port 1, port 5 structure figure 11-1. the i/o port block diagram note : all of the latch output circuits are push-pull structures. port0 structure pur p0ur pin int. bus pin int. bus pur port2 structure lcd waveform p2seg p2ur pin pin int. bus pur port2 structure pur port2 structure lcd waveform lcd waveform p2seg p2ur pull-up pin output latch pnm, pnur input bus pnm output bus
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 113 v1.4 i/o port function table port/pin i/o function description remark general-purpose input function external interrupt (int0~int1) see p0.0~p0.1 i wakeup for power down mode see general-purpose input/output function p1.0~p1.4 i/o wakeup for power down mode general-purpose input function p2.0~p2.7 i lcd segment general-purpose input/output function p5.0 i/o sio clock pin. i/o general-purpose input/output function p5.1 i sio data input pin. p5m.1 must be set ?0? i/o general-purpose input/output function p5.2 o sio data output pin. p5m.1 must be set ?1? p5.3~p5.4 i/o general-purpose input/output function table 11-1. i/o function table pull-up resistor (p n ur) register p n ur initial value = 0000 0000 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p n ur p n 7r p n 6r p n 5r p n 4r p n 3r p n 2r p n 1r p n 0r r/w r/w r/w r/w r/w r/w r/w r/w p n ur : the n expressed 0, 1, 2, 5. p n 7r ~ p n 0r: pull-up resistor control bit. 0 = without pull up resistor 1 = with pull up resistor.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 114 v1.4 i/o port mode the port direction is decided by p n m register. port 0 is always input mode. port 1 and port 5 can select input or output direction. p1m initial value = xx00 0000 0c1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1m 0 0 0 p14m p13m p12m p11m p10m - - - r/w r/w r/w r/w r/w p10m~p15m: p1.0~p1.5 i/o direction contro l bit. 0 = input mode, 1 = output mode. p5m initial value = 0000 0000 0c5h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p5m 0 0 0 p54m p53m p52m p51m p50m - - - r/w r/w r/w r/w r/w p50m~p54m: p5.0~p5.4 i/o direction contro l bit. 0 = input mode, 1 = output mode. the each bit of p n m is set to ?0?, the i/o pin is input mode. the each bit of p n m is set to ?1?, the i/o pin is output mode. the p n m registers are read/write bi-direction registers. users can program them by bit control instructions (b0bset, b0bclr). example: i/o mode selection. clr p1m ; set all ports to be input mode. clr p5m mov a, #0ffh ; set all ports to be output mode. b0mov p1m, a b0mov p5m, a b0bclr p1m.1 ; set p1.1 to be input mode. b0bset p1m.1 ; set p1.1 to be output mode.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 115 v1.4 the port2 discription the port 2 is input pins and shared with seg24~seg31 lcd driv er pins. the port2 must work without lcd. to set the bit p2seg = ?1?, the port 2 input function will be enabl ed. input data from port 2 is by p2 data register. figure 11-2. port 2 block diagram example: enable port 2 input function. step1: connect vlcd1 to vlcd step2: set p2seg=1 b0bset fp2seg ; disable pin 45 ~ 52 lcd driver. step3: now the port 2 general input function is enable. user can input data by port 2. b0mov a, p2 ; input port 2 value to buf. b0mov buf, a pin int. bus pur port2 structure lcd waveform p2seg p2ur pin pin int. bus pur port2 structure pur port2 structure lcd waveform lcd waveform p2seg p2ur
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 116 v1.4 i/o port data register p0 initial value = xxxx xxx0 0d0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0 - - - - - - p01 p00 - - - - - - r r p1 initial value = xx00 0000 0d1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1 - - - p14 p13 p12 p11 p10 - - - r/w r/w r/w r/w r/w p2 initial value = 0000 0000 0d2h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p2 p27 p26 p25 p24 p23 p22 p21 p20 r r r r r r r r p5 initial value = xxx0 0000 0d5h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p5 - - - p54 p53 p52 p51 p50 - - - r/w r/w r/w r/w r/w example: read data from input port. b0mov a, p0 ; read data from port 0 b0mov a, p1 ; read data from port 1 b0mov a, p5 ; read data from port 5 example: write data to output port. mov a, #55h ; write data 55h to port 1 and port 5 b0mov p1, a b0mov p5, a example: write one bit data to output port. b0bset p1.3 ; set p1.3 to be ?1?. b0bclr p1.3 ; set p1.3 and p5.1 to be ?0?. b0bclr p5.1 example: port bit test. b0bts1 p0.0 ; bit test 1 for p0.0 . b0bts0 p1.1 ; bit test 0 for p1.1
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 117 v1.4 1 1 1 2 2 2 lcd driver there are 4 common pins and 32 segment pins in the sn8p 1900. the lcd scan timing is 1/4 duty and 1/2,1/3 bias structure to yield 128 dots lcd driver. of these pins, eight segment pins ar e shared with port 2 and p2/seg functions can be selected by programming lcdm1 register. lcdm1 register lcdm1 register initial value = xx0x 00x1 0cbh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lcdm1 - - lcdbnk - lcdenb bias - p2seg - - r/w - r/w r/w - r/w p2seg: port2 control bit. 0 = segment pins 1 = general purpose i/o pins. bias: lcd bias control bit. 0 = 1/3 bias 1 = 1/2 bias lcdenb: lcd driver enable control bit. 0 = disable 1 = enable. lcdbnk: lcd blank control bit. 0 = normal display 1 = all of the lcd dots off. note: connect vlcd and vlcd1 to the same voltage.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 118 v1.4 in following diagram, in order to get suitable contrast level of lcd panel, users can add external resistor to bias pin (v1, v2, v3) to adjust bias voltage and lcd drive current. too mu ch or less current makes the lcd to bring remnant images. in normal condition, the external bias resistor va lue is 100k ohm. users can connect a resistor between vlcd and vdd to adjust the voltage level at vlcd pin or just connect vlcd to vdd directly. figure 12-1. example of circuit at each bias
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 119 v1.4 lcd timing f-frame = external low clock / 512 ex. external low clock is 32768hz. the f-frame is 32768hz/512 = 64hz . note: the clock source of lcd dr iver is external low clock. com0 com1 com2 com3 seg0 1 frame 1 frame lcd clock vlcd v3 = v2 v1 lcd off off on on vlcd v1 figure 12-2. lcd drive waveform, 1/4 duty, 1/2 bias
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 120 v1.4 com0 com1 com2 com3 seg0 1 frame 1 frame lcd clock vlcd v3 v1 lcd off off on on v2 vlcd v3 v1 v2 figure 12-3. lcd drive waveform, 1/4 duty, 1/3 bias
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 121 v1.4 lcd ram location ram bank 15?s address vs. common/segment pin location bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 com0 com1 com2 com3 - - - - seg 0 00h.0 00h.1 00h.2 00h.3 - - - - seg 1 01h.0 01h.1 01h.2 01h.3 - - - - seg 2 02h.0 02h.1 02h.2 02h.3 - - - - seg 3 03h.0 03h.1 03h.2 03h.3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - seg 14 0eh.0 0eh.1 0e h.2 0eh.3 - - - - seg 15 0fh.0 0fh.1 0fh.2 0fh.3 - - - - seg 16 10h.0 10h.1 10h.2 10h.3 - - - - seg 17 11h.0 11h.1 11h.2 11h.3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - seg 29 1dh.0 1dh.1 1d h.2 1dh.3 - - - - seg 30 1eh.0 1eh.1 1e h.2 1eh.3 - - - - seg 31 1fh.0 1fh.1 1fh.2 1fh.3 - - - - example: enable lcd function. enable the segment pin shared with port2. b0bclr fp2seg ; enable seg24~seg31 now all lcd pins are enabled. set the lcd control bi t (lcdenb) and program lcd ram to display lcd panel. b0bset flcdenb ; lcd driver.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 122 v1.4 1 1 1 3 3 3 charge-pump, pgia and adc overview the sn8p1900 has a built-in voltage charge-pump/regulat or (cpr) to support a stable voltage 3.8v from pin avddr with maximum 10ma current driving capacity. this cp r provides stable voltage for internal circuits (pgia, adc) and external sensor (load cell or thermistor). the sn8p1900 series also integrated ? analog-to-digital converters (adc) to achieve 16-bit performance and up to 62500-step resolution. the adc has 3 different input channel modes: (1) three fully differential inputs (2) two fu lly differential inputs and two single-ended inputs (3) one differential input and four single-ended inputs. this adc is optimized for measuring low-level unipolar or bipolar signals in weight scale and medical applications. a very low noise chopper-stabilized programmable gain instrumentation amplifier (pgia) with selectable gains of 1x, 16x, 32x, 64x, and 128x in the adc to accommodate these applications. analog input figure 13-1 illustrates a block diagram of the pgia and adc module. the front end consists of a multiplexer for input channel selection, a pgia (programmable gain instrumentation amplifier), and the ? adc modulator. to obtain maximum range of adc output, the adc maximum input signal voltage v (x+, x-) should be close to but can?t over the reference voltage v(r+, r-), choosing a suitable reference voltage and a suitable gain of pgia can reach this purpose. the relative control bits are rvs [1:0 ] bits (reference voltage selection) in adcm register and gs[2:0] bits (gain selection) in ampm register. figure 13-1 block diagram of adc module note 1: in figure 13-1, the low pa ss filter (r1, r2 and c) will filt er out chopper frequency of pgia. note 2: the recommend values of r1, r2 are 100k ? and c is 0.1 f. these resistances and capacitor need to place as close chip as possible. anlaog input mux chopper stabilized pgia gain= 1,16,32,64,128 ai3+ ai3- ai2+ ai2- ao+ ao- analog mux x- x+ reference mux r- r+ differential second o rder delta-sigma modulator programmable sinc fir filter 1.2v bandgap reference charge pump regulator & voltage detector adch/l avddcp avddr agnd acm c+ c- vdd gnd adcks cpcks ampcks ai1+ ai1- battery monitor acm unit gain buffer
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 123 v1.4 voltage charge pump / regulator (cpr) sn8p1900 is built in a cpr which can provide a stable 3.8v (pin avddr) with maximum 10ma current driving capacity. register cpm can enable or disable cpr and cont rols cpr working mode, another register cpcks sets cpr working clock to 20khz. because the power of pgia and adc is come from cpr, turn on cpr (cprenb = 1) first before enabling pgia and adc. in addi tion, the cpr will need at least 10ms for output voltage stabilization after set cprenb to high. cpm-charge pump mode register 095h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cpm - - - - cpsts cpauto cpon cprenb - - - - r r/w r/w r/w cprenb: charge pump / regulator function enable control bit. 0 = disable charge pump and regulator, 1 = enable charge pump and regular. note: 10ms delay is necessary for output vo ltage stabilization after set cprenb = ?1?. cpon: change pump always on function control bit (cprenb must = ?1?) 0 = charge pump on / off controlled by bit cpauto. 1 = always turn on the charge pump regulator. cpauto: charge pump auto mode function control bit 0 = disable charge pump auto mode. 1 = enable charge pump auto mode. cpsts: charge-pump status bit in auto mode (only available when cpauto = ?1?) 0 = charge-pump is off in auto mode. 1 = charge-pump is on in auto mode. note 1: all current consumptions from avddr (inc luding pgia and adc) will time 2, when charge pump was enabled.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 124 v1.4 bit cprenb, cpon, and cpauto are charge-pump working mode control bit. by these three bits, charge-pump can be set as off, always on, or auto mode. cprenb cpon cpauto charge-pump status regulator status cpsts avddr pgia, adc function 0 x x off off n/a 0v not available 1 0 0 off on n/a see note1 see note1 1 0 1 auto mode on 0/1 3.8v available 1 1 0 on on n/a 3.8v available 1 1 1 reserved (don?t set this mode) in auto mode, charge-pump on/off depended on vdd voltage. auto-mode description: cprenb cpon cpauto vdd charge-pump status cpsts regulator status avddr output pgia, adc function >4.1v off 0 on 3.8v available 1 0 1 ?? 4.1v on 1 on 3.8v available note 1: when charge-pump is off and regulator is on, vdd voltage must be higher than 3.9v to make sure avddr output voltage, pgia, and adc functions are working well. cprenb cpon cpauto vdd charge-pump status regulator status avddr output pgia, adc function >4.1v off on 3.8v available 1 0 0 ?? 4.1v off on unknown not available note 2: for normally application, set cp as auto mode (cpauto = 1) is strongly recommended. note 3: if vdd is higher than 5.0v, don?t set charge-pump as always on mode.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 125 v1.4 cpcks-charge pump clock register 096h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cpcks cpcks7 cpcks6 cpcks5 cpcks4 cpcks3 cpcks2 cpcks1 cpcks0 w w w w w w w w w cpcks [7:0] register sets the charge-pump working clock; the suggestion charge-pump clock is 20k hz.@ 4mhz refer to the following table for cpcks [7:0] register value setting in different fosc frequency. charge-pump clock= (fosc / (256-cpcks [7:0])) / 2 cpcks [7:0] f osc cp working clock 156 4m (4m / 100) / 2 = 20k 56 8m (8m / 200) / 2 = 20k note: in general application, cp working clock is 20k hz.. example: charge-pump setting (fosc = 4m x?tal) @cpreg_init: mov a, #04h xb0mov cpm, a ; set charge-pump as auto mode mov a, #0156 xb0mov cpcks, a ; set cpcks = 156 for cp working clock = 20k @ 4m x?tal @cp_enable: xb0bset fcprenb ; enable char ge-pump / regulator function @delay_10ms: call @wait_10ms ; delay 10ms for charge-pump stabilize ? ?
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 126 v1.4 pgia -programmable gain instrumentation amplifier sn8p1900 includes a low noise chopper- stabilized programmable gain instrumentat ion amplifier (pgia) with selection gains of 1x, 16x, 32x, 64x, and 128x by register ampm. the pgia also provides three types channel selection mode: (1) three fully differential inputs (2) two fully differential inputs and two single-ended inputs (3) one differential input and four single-ended inputs, it was defined by register ampchs. ampm- amplifier mode register 090h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ampm - - fds1 fds0 gs2 gs1 gs0 ampenb - - r/w r/w r/ w r/w r/w r/w ampenb: pgia function enable control bit. 0 = disable pgia function 1 = enable pgia function gs [2:0]: pgia gain selection control bit gs [2:0] pgia gain 000 16 001 32 010 64 011 128 100,101,110 reserved 111 1 fds [1:0]: pgia chopper frequency setting set fds [1:0] = ? 10 ? all the time. ampcks- pgia clock selection 092h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ampcks ampcks7 ampcks6 am pcks5 ampcks4 ampcks3 am pcks2 ampcks1 ampcks0 w w w w w w w w ampcks [7:0] register sets the pgia working clock, the suggestion pgia clock is 4k hz. refer to the following table for ampcks [7:0] register value setting in different fosc frequency. pgia clock= (fosc / (256-ampcks [7:0])) / 8 ampcks [7:0] f osc pgia working clock 131 4m (4m / 125) / 8 = 4k 6 8m (8m / 250) / 8 = 4k note: in general application, pgia working clock is 4k hz..
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 127 v1.4 ampchs-pgia channel selection 091h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ampchs - - - - - chs2 chs1 chs0 - - - - - r/w r/w r/w chs [2:0]: pgia channel selection chs [2:0] selected channel v (ao+, ao-) output input-signal type 000 ai1+, ai1- v (ai1+, ai1-) pgia gain differential 001 ai2+, ai2- v (ai2+, ai2-) pgia gain differential 010 ai3+, ai3- v (ai3+, ai3-) pgia gain differential 011 ai2+, acm v (ai2+, acm) pgia gain single-ended 100 ai2-, acm v (ai2-, acm) pgia gain single-ended 101 ai3+, acm v (ai3+, acm) pgia gain single-ended 110 ai3-, acm v (ai3-, acm) pgia gain single-ended 111 acm, acm v (acm, acm) pgia gain input-short note 1: v (ai1+, ai1-) = (ai1+ voltage - ai1- voltage) note 2: v (ai2-, ac m) = (ai2- voltage - acm voltage) note 3: the purpose of input-short mode is only for pgia offset testing. note 4: when cpr is disable or system in stop mode , signal on analog input pins must be zero (?0?v, including ai1+, ai1-, ai2+, ai2-, ai3+, ai3-, x+ , x-, r+ and r-) or it will cause the current consumption from these pins. figure 13-2 channel selection diagram figure 13-3 input short mode pgia ai1+ ai1- ai3+ ai2- ai3- ai2+ acm=1.2v ao+ ao- sn8p1900 pgia ai1+ ai1- ai3+ ai2- ai3- ai2+ acm=1.2v ao+ ao- sn8p1900
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 128 v1.4 figure 13-4 channel selection: ai2+, acm figure 13-5 channel selection: ai2-, acm figure 13-6 channel configuration m ode one: 3 fully differential inputs pgia ai1+ ai1- ai3+ ai2- ai3- ai2+ acm=1.2v ao+ ao- sn8p1900 pgia ai1+ ai1- ai3+ ai2- ai3- ai2+ acm=1.2v ao+ ao- sn8p1900 1 2 3 4 1 2 3 4 1 2 3 4 ai1+ ai1- ai2- ai2+ ai3+ ai3+ avddr acm
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 129 v1.4 figure 13-7 channel configuration mode two: 2 fully differential inputs and 2 single-ended inputs figure 13-8 channel configuration mode three: 1 fully differential input and 4 single-ended inputs 1 2 3 4 1 2 3 4 ai1+ ai1- ai2- ai2+ ai3+ ai3+ avddr acm 1 2 3 4 ai1+ ai1- ai2- ai2+ ai3+ ai3+ avddr acm
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 130 v1.4 example: pgia setting (fosc = 4m x?tal) @cpreg_init: ; enable charge-pump/regulator before pgia working mov a, #04h xb0mov cpm, a ; set charge-pump as auto mode mov a, #0156 xb0mov cpcks, a ; set cpcks = 156 for cp working clock = 20k @ 4m x?tal @cp_enable: xb0bset fcprenb ; enable char ge-pump / regulator function @delay_10ms: call @wait_10ms ; delay 10ms for charge-pump stabilize @pgia_init: mov a, #026h xb0mov ampm, a ; selected pgia gain=128, and fds [1:0]= ?10? mov a, #0131 xb0mov ampcks, a ; set ampcks = 131 for pgia working clock = 4k @ 4m x?tal mov a, #02h xb0mov ampchs, a ; selected pgia input channel= ai3+, ai3- @pgia_enable : xb0bset fampenb ; enable pgia function ? ; v (ao+, ao-) output = v (ai3+, ai3-) x 128 note 1: enable charge-pump/regulator before pgia working note 2: please set pgia relative registers first, then enable pgia function bit.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 131 v1.4 16-bit adc adcm- adc mode register 093h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adcm - - - - - rvs1 rvs0 adcenb - - - - - r/w r/w r/w adcenb: adc function control bit: 0 = disable 16-bit adc, 1 = enable 16-bit adc rvs [1:0]: adc reference voltage selection ad reference voltage ad channel input rvs [1:0] ref+ ref- adcin+ adcin- note 00 r+ r- x+ x- v (x+, x-) < v (r+, r-) 01 reserved 10 2.4v 1.2v x+ x- v (x+, x-) < 1.2v 11 2.4v 1.2v vdd / 3 vdd / 6 adc input = 1/6 vdd for battery monitor note 1: the adc conversion data is combined with adcdh and adcdl register in 2?s compliment with sign bit numerical format, and bi t adcb15 is the sign bit of adc data. refer to following formula to calculate adc conversion data value. 31250 ) ( ) ( ) ( ) ( ) ( ) ( 31250 ) ( ) ( ) ( ) ( ) ( ) ( x ref ref adcin adcin iondata adcconvers adcin adcin x ref ref adcin adcin iondata adcconvers adcin adcin ? ? + ? ? + ? = ? ? < + ? ? + ? ? + + = ? ? > + note2: the internal 2.4v and 1.2v reference voltage are generated from band gap reference voltage. figure 13-9 measure v(x+, x-) voltage by external reference voltage. r+ 2.4v 1.2v r- adc ref+ ref- adcin+ adcin- rvs[1:0]=00 x+ x- vdd vss 4r r r vdd/3 vdd/6
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 132 v1.4 figure 13-10 measure v(x+, x-) voltage by internal 2.4v and 1.2v reference voltage figure 13-11 measure vdd (battery voltage) by internal 2.4v and 1.2v reference voltage note : when cpr is disable or system in stop mode , signal on analog input pins must be zero (?0?v, including ai1+, ai1-, ai2+, ai2-, ai3+, ai3-, x+, x-, r+ and r-) or it will cause the current consumption from these pins. r+ 2.4v 1.2v r- adc ref+ ref- adcin+ adcin- rvs[1:0]=10 x+ x- vdd vss 4r r r vdd/3 vdd/6 r+ 2.4v 1.2v r- adc ref+ ref- adcin+ adcin- rvs[1:0]=11 x+ x- vdd vss 4r r r vdd/3 vdd/6
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 133 v1.4 adcks- adc clock register 094h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adcks adcks7 adcks6 adcks5 adcks4 adcks3 adcks2 adcks1 adcks0 w w w w w w w w adcks [7:0] register sets the adc working clock, refer the following table for adcks [7:0] regist er value setting in different fosc frequency. adc clock= (fosc / (256-adcks [7:0])) / 2 adc clock = 200k setting adcks [7:0] f osc adc working clock 246 4m (4m / 10) / 2 = 200k 236 8m (8m / 20) / 2 = 200k adc clock = 100k setting adcks [7:0] f osc adc working clock 236 4m (4m / 20) / 2 = 100k 216 8m (8m / 40) / 2 = 100k adc clock = 80k setting adcks [7:0] f osc adc working clock 231 4m (4m / 25) / 2 = 80k 206 8m (8m / 50) / 2 = 80k note: in general application, adc working clock is 100k hz.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 134 v1.4 adcdl- adc low-byte data register 098h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adcdl adcb7 adcb6 adcb 5 adcb4 adcb3 a dcb2 adcb1 adcb0 r r r r r r r r adcdh- adc high-byte data register 099h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adcdh adcb15 adcb14 adcb13 adcb12 adcb11 adcb10 adcb8 adcb9 r r r r r r r r adcdl [7:0]: output low byte data of adc conversion word. adcdh [7:0]: output high byte data of adc conversion word. . note1: adcdl [7:0] and adcdh [7:0] are both read only registers. note2: the adc conversion data is combined wi th adcdh, adcdl in 2?s compliment with sign bit numerical format, and bit adcb15 is the sign bit of adc data. adcb15=0 means data is positive value, adcb15=1 means data is negative value. note3: the positive full-scale-output val ue of adc conversion is 0x7a12. note4: the negative full-scale-output value of adc conversion is 0x85ee. note5: because of the adc design limitation, the ad c linear range is +28125~-28125 (decimal). the max adc output must keep inside this range. adc conversion data (2?s compliment, hexadecimal) decimal value 0x7a12 31250 ? ? 0x4000 16384 ? ? 0x1000 4096 ? ? 0x0002 2 0x0001 1 0x0000 0 0xffff -1 0xfffe -2 ? ? 0xf000 -4096 ? ? 0xc000 -16384 ? ? 0x85ee -31250
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 135 v1.4 dfm-adc digital filter mode register 097h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dfm - - - - wrs1 wrs0 stod drdy - - - - r/w r/w r/w r/w drdy: adc data ready bit. ?1? = adc output (update) new c onversion data to adcdh, adcdl. ?0? = adcdh, adcdl conversion data are not ready. stod: stop output adc data. ?0? = adc is in continuous mode; old data w ill be replaced continuously by the new one. ?1? = no more new conversion word will update to adcdh/adcdl. wrs [1:0]: adc output word rate selection: output word rate wrs [1:0] adc clock = 200k adc clock = 100k adc clock = 80k 00 50 hz 25 hz 20 hz 01 25 hz 12.5 hz 10 hz 10 12.5 hz 6.25 hz 5 hz 11 6.25 hz 3.125 hz 2.5 hz note 1: when stod=0, the adc is designed for continuous mode, so it needn?t read each conversion data every time. user only needs to read the data when conversion result is required. note that if the conversion data is not read immediately, it could be lost and be replaced by the next new conversion data. note2: when stod = 1, although no more conversion wo rd will update to adc output buffer, but adc is still working and will output conv ersion word when stod= 0. note 3: ac power 50 hz noise will be filt er out when output word rate = 25hz note 4: ac power 60 hz noise will be filt er out when output word rate = 20hz note 5: both ac power 50 hz and 60 hz noise w ill be filter out when output word rate = 10hz note 6: clear bit drdy a fter got adc data or this bit will keep high all the time.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 136 v1.4 example: charge-pump, pgia and adc setting (fosc = 4m x?tal) @cpreg_init: ;enable charge-pump/regulator before pgia, adc working mov a, #04h xb0mov cpm, a ; set charge-pump as auto mode mov a, #0156 xb0mov cpcks, a ; set cpcks = 156 for cp working clock = 20k @ 4m x?tal @cp_enable: xb0bset fcprenb ; enable char ge-pump / regulator function @delay_10ms: call @wait_10ms ; delay 10ms for charge-pump stabilize @pgia_init: mov a, #026h xb0mov ampm, a ; selected pgia gain=128, and fds [1:0]= ?10? mov a, #0131 xb0mov ampcks, a ; set ampcks = 131 for pgia working clock = 4k @ 4m x?tal mov a, #02h xb0mov ampchs, a ; selected pgia input channel= ai3+, ai3- @pgia_enable : xb0bset fampenb ; enable pgia function ; v (ao+, ao-) output = v (ai3+, ai3-) x 128 @adc_init: mov a,#00h ; selection adc reference voltage = v(r+, r-) xb0mov adcm ; selection adc reference voltage = v(r+, r-) mov a, #0246 xb0mov adcks, a ; set adcks = 246 for adc working clock = 200k @ 4m x?tal mov a, #00h xb0mov dfm, a ; set adc as continuous mode and wrs [1:0] = ?00? 50 hz @adc_enable: xb0bset adcenb ; enable adc function @adc_wait: xb0bts1 fdrdy ; check adc output new data or not jmp @adc_wait ; wait for bit drdy = 1 @adc_read: ; output adc conversion word xb0bclr fdrdy xb0mov a, adcdh b0mov data_h_buf, a ; move adc c onversion high byte to data buffer. xb0mov a, adcdl b0mov data_l_buf, a ; move adc c onversion low byte to data buffer. ? ? note 1: enable charge-pump/regulator before pgia working note 2: please set adc relative registers first, than enable adc function bit.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 137 v1.4 1 1 1 4 4 4 application circuit scale (load cell) application circuit avddcp c+ vdd c- vss lxin lxout xin xout 47u 10u 10u 4m x't a l 32k x't a l p0.0 p0.1 rst p1.0 10k 104 20pf p5.0 p1.3 p1.1 vss avss acm 20pf 20pf 20pf 47u avddr 10u r- r+ 104 104 ao- ao+ x - x+ 100k 100k 0.1uf ai2- ai2+ ai3- ai3+ ai1- ai1+ bridge ty pe sensor avddr com 3 seg 0 lcd com 2 p5.1 p5.2 serial data interface p1.2 com 1 com 0 seg 1 seg 31 seg 30 ............................................ vlcd vdd 104 104 104 vdd vlcd1 vdd e+ 100 e+
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 138 v1.4 thermometer application circuit thermopile avddr thermistor avddcp c+ vdd c- vss lxin lxout xin xout 47u 10u 10u 4m x't a l 32k x't a l p0.0 p0.1 rst p1.0 10k 104 20pf p5.0 p1.3 p1.1 vss avss acm 20pf 20pf 20pf 47u avddr 10u r- r+ 104 104 ao- ao+ x - x+ 100k 100k 0.1uf ai3- ai3+ ai2+ com 3 seg 0 lcd com 2 avddr p5.1 p5.2 serial data interface p1.2 com 1 com 0 seg 1 seg 31 seg 30 ............................................ vlcd vdd 104 104 104 vdd vlcd1 vdd acm 100
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 139 v1.4 1 1 1 5 5 5 instruction set table field mnemonic description c dc z cycle mov a,m a m - - 1 m mov m,a m a - - - 1 o b0mov a,m a m (bank 0) - - 1 v b0mov m,a m (bank 0) a - - - 1 e mov a,i a i - - - 1 b0mov m,i m i, m = only supports 0x80~0x87, (e.g. r, y, z , rbank ,pflag??.) - - - 1 xch a,m a m - - - 1 b0xch a,m a m (bank 0) - - - 1 movc r, a rom [y,z] - - - 2 adc a,m a a + m + c, if occur carry, then c=1, else c=0 1 a adc m,a m a + m + c, if occur carry, then c=1, else c=0 1 r add a,m a a + m, if occur carry, then c=1, else c=0 1 i add m,a m a + m, if occur carry, then c=1, else c=0 1 t b0add m,a m (bank 0) m (bank 0) + a, if occur carry, then c=1, else c=0 1 h add a,i a a + i, if occur carry, then c=1, else c=0 1 m sbc a,m a a - m - /c, if occur borrow, then c=0, else c=1 1 e sbc m,a m a - m - /c, if occur borrow, then c=0, else c=1 1 t sub a,m a a - m, if occur borrow, then c=0, else c=1 1 i sub m,a m a - m, if occur borrow, then c=0, else c=1 1 c sub a,i a a - i, if occur borrow, then c=0, else c=1 1 daa to adjust acc?s data format from hex to dec. - - 1 mul a,m r, a a * m, the lb of product stored in acc and hb stored in r register. zf affected by acc. - - 2 and a,m a a and m - - 1 l and m,a m a and m - - 1 o and a,i a a and i - - 1 g or a,m a a or m - - 1 i or m,a m a or m - - 1 c or a,i a a or i - - 1 xor a,m a a xor m - - 1 xor m,a m a xor m - - 1 xor a,i a a xor i - - 1 swap m a (b3~b0, b7~b4) m(b7~b4, b3~b0) - - - 1 p swapm m m(b3~b0, b7~b4) m(b7~b4, b3~b0) - - - 1 r rrc m a rrc m - - 1 o rrcm m m rrc m - - 1 c rlc m a rlc m - - 1 e rlcm m m rlc m - - 1 s clr m m 0 - - - 1 s bclr m.b m.b 0 - - - 1 bset m.b m.b 1 - - - 1 b0bclr m.b m(bank 0).b 0 - - - 1 b0bset m.b m(bank 0).b 1 - - - 1 cmprs a,i zf,c a - i, if a = i, then skip next instruction - 1 + s b cmprs a,m zf,c a ? m, if a = m, then skip next instruction - 1 + s r incs m a m + 1, if a = 0, then skip next instruction - - - 1 + s a incms m m m + 1, if m = 0, then skip next instruction - - - 1 + s n decs m a m - 1, if a = 0, then skip next instruction - - - 1 + s c decms m m m - 1, if m = 0, then skip next instruction - - - 1 + s h bts0 m.b if m.b = 0, then skip next instruction - - - 1 + s bts1 m.b if m.b = 1, then skip next instruction - - - 1 + s b0bts0 m.b if m (bank 0).b = 0, then skip next instruction - - - 1 + s b0bts1 m.b if m (bank 0).b = 1, then skip next instruction - - - 1 + s jmp d pc15/14 rompages1/0, pc13~pc0 d - - - 2 call d stack pc15~pc0, pc15/14 rompages1/0, pc13~pc0 d - - - 2 m ret pc stack - - - 2 i reti pc stack, and to enable global interrupt - - - 2 s push to push working regist ers (080h~087h) into buffers - - - 1 c pop to pop working regist ers (080h~087h) from buffers 1 nop no operation - - - 1 table 15-1. instruction set table of sn8p1900 note: any instruction that read/write from 0scm, will add an extra cycle.
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 140 v1.4 1 1 1 6 6 6 electrical characteristic absolute maximum rating supply voltage (v dd )??????????????..????????????? - 0.3v ~ 6.0v input in voltage (v in )???????????..???.???????? v ss - 0.2v ~ v dd + 0.2v operating ambient temperature (t opr )??????????????????? -20 c ~ + 70 c storage ambient temperature (t stor )???????..???.???????? ?30 c ~ + 125 c electrical characteristic (all of voltages refer to v ss , v dd = 5.0v,f osc = 4mhz, ambient temperature is 25 c unless otherwise note.) parameter sym. description min. typ. max. unit normal mode, v pp = v dd 2.4 5.0 5.5 operating voltage v dd programming mode, v pp = 12.5v - 6.0 - v otp programming voltage v pp otp programming voltage - 12.5 - v ram data retention voltage v dr - 2 - v internal por v por v dd rise rate to ensure internal power-on reset - 0.05 - v/ms vil1 all input pins except those specified below v ss - 0.3v dd v vil2 input with schmitt trigger buffer v ss - 0.2v dd v vil3 reset pin; xin (in rc mode) v ss - 0.2v dd v input low voltage vil4 xin (in x?tal mode) v ss - 0.3v dd v vih1 all input pins except those specified below 0.7v dd - v dd v vih2 input with schmitt trigger buffer 0.8v dd - v dd v vih3 reset pin; xin (in rc mode) 0.9v dd - v dd v input high voltage vih4 xin (in x?tal mode) 0.7v dd - v dd v reset pin leakage current i lekg v in = v dd - - 1 ma i/o port pull-up resistor r up v in = v ss , v dd = 5v - 100 - k ? i/o port input leakage current i lekg pull-up resistor disable, v in = v dd - - 1 ma all port source current i o h v op = v dd - 0.5v - 15 - ma sink current i o l v op = v ss + 0.5v - 15 - int n trigger pulse width t int 0 int0 ~ int1 interrupt request pulse width 2/f cpu - - cycle vdd= 5v 4mhz - 3 5 ma vdd= 3v 4mhz - 1 2 ma idd1 run mode (low power disable) vdd= 3v 32768hz - 40 - ua vdd= 5v 4mhz - 2 3 ma idd2 run mode (low power enable) vdd= 3v 4mhz - 0.7 1.4 ma vdd= 5v 32768hz - 50 75 ua idd3 slow mode (stop high clock) vdd= 3v 32768hz - 15 25 ua vdd= 5v - 1 2 ua idd4 sleep mode vdd= 3v - - 1 ua vdd= 5v 32768hz - 30 50 ua supply current (disable analog part / lcd) idd5 green mode (stop high clock) vdd= 3v 32768hz 10 15 ua lvd detect level v lvd internal por detect level - 1.8 - v
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 141 v1.4 (all of voltages refer to avddr=3.8v f osc = 4mhz, ambient temperature is 25 c unless otherwise note.) parameter sym. description min. typ. max. unit analog to digital converter operating current i dd_adc run mode @ avddr = 3.8v 800 1000 a power down current i pdn stop mode @ avddr = 3.8v 0.1 1 a conversion rate f smp adcks: 100khz 25 sps vref1 r+, r- input voltage 0.4 2.0 v reference voltage input voltage vref2 differential voltage in r+ and r- 0.3 v differential non-linearity dnl adc range ? 28125 0.5 0.5 lsb integral non-linearity inl adc range ? 28125 1 4 lsb no missing code nmc adc range ? 28125 16 bit noise free code nfc adc range ? 28125 14 16 bit effective number of bits enob adc range ? 28125 14 16 bit adc input range v ain 0.4 2.0 v pgia current consumption i dd_pgia run mode @ avddr = 3.8v 300 500 a power down current i pdn stop mode @ avddr = 3.8v 0.1 a input offset voltage vos 2 uv bandwidth bw 100 hz pgia input range vopin avddr = 3.8v 0.4 2 v pgia output range vopout avddr = 3.8v 0.4 2 v charge pump regulator supply voltage v cps normal mode 2.4 5.5 v regulator output voltage v cpo avddr pin output voltage 3.650 3.800 3.950 v analog common voltage v acm acm pin voltage 1.15 1.2 1.25 v reference voltage temperature coefficient t acm acm pin voltage 50 ppm/ j regulator output current capacity i va+ avddr pin driving current 10 ma quiescent current i qi 700 a v acm driving capacity i src acm pin driving current 10 a v acm sinking capacity i snk acm pin sink current 1 ma
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 142 v1.4 1 1 1 7 7 7 package information lqfp64:
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 143 v1.4 dimension (mm) dimension (mil) symble min. nom. max. min. nom. max. a 1.60 63 a1 0.05 1.40 0.15 2 55 6 a2 1.36 0.22 1.45 35 9 57 b 0.17 0.22 0.27 7 8 11 b1 0.17 0.23 7 12 c 0.09 0.20 4 8 c1 0.09 0.16 4 6 d 11.75 12.00 12.25 463 473 483 d1 9.95 10.00 10.05 392 394 396 e 11.75 12.00 12.25 463 473 483 e1 9.95 10.00 10.05 392 394 396 [e] 0.50 20 l 0.45 0.60 0.75 18 24 30 l1 0.9 1 1.1 39 r1 0.08 3 r2 0.08 0.20 3 8 y 0.075 3 0 3.5 7 0 3.5 7 1 0 0 2 11 12 13 11 12 13 3 11 12 13 11 12 13
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 144 v1.4 lqfp80
SN8P1908 / sn8p1909 8-bit mcu build-in 16-bit adc + pgia + ch arge-pump regulator + 128 dots lcd driver sonix technology co., ltd page 145 v1.4 sonix reserves the right to make change without further notic e to any products herein to im prove reliability, function or design. sonix does not assume any liability arising out of th e application or use of any product or circuit described herein; neither does it convey any license under its patent rights no r the rights of others. sonix products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other applicati on in which the failure of the sonix product could create a situation where personal injury or death may occur. s hould buyer purchase or use sonix products for any such unintended or unauthorized application. buye r shall indemnify and hold sonix and its officers , employees, subsidiaries, affiliates and distributors harmless against all claims, cos t, damages, and expenses, and reasonabl e attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that sonix was negligent regarding the design or manufacture of the part. main office: address: 9f, no. 8, hsien cheng 5th s t, chupei city, hsinchu, taiwan r.o.c. tel: 886-3-551 0520 fax: 886-3-551 0523 taipei office: address: 15f-2, no. 171, song ted road, taipei, taiwan r.o.c. tel: 886-2-2759 1980 fax: 886-2-2759 8180 hong kong office: address: flat 3 9/f energy plaza 92 gr anville road, tsimshatsui east kowloon. tel: 852-2723 8086 fax: 852-2723 9179 technical support by email: sn8fae@sonix.com.tw

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